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m68hc08 microcontrollers freescale.com mc68hc908ey16 mc68hc908ey8 data sheet mc68hc908ey16 rev. 10 10/2005

mc68hc908ey16 ? mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc908ey16 mc68hc908ey8 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com refer to the revision history for a summary of changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location.
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 4 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 5 list of chapters chapter 1 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 chapter 3 analog-to-digital converter ( adc) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 4 bemf counter module (b emf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 chapter 5 configuration registers (c onfig1 and config2) . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 computer oper ating properly (cop) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 7 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 8 internal clock generat or (icg) module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 chapter 9 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 10 keyboard interrupt (kbd) modu le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 chapter 11 low-voltage inhibit (lvi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 12 input/output (i/o) po rts (ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 chapter 13 enhanced serial communi cations interface (esci) module. . . . . . . . . . . . . . . 125 chapter 14 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 chapter 15 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 chapter 16 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 chapter 17 timer interface a (t ima) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 chapter 18 timer interface b (t imb) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 chapter 19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 chapter 20 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 chapter 21 ordering informat ion and mechanical specifications . . . . . . . . . . . . . . . . . . . . 253 appendix a mc68hc908ey8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
list of chapters mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 6 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.2 oscillator pins (ptc4/osc1 and ptc3/osc2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.5 analog power supply/reference pins (v dda , v refh , v ssa and v refl ) . . . . . . . . . . . . . . . 23 1.5.6 port a i/o pins (pta6/ss , pta5/spsck, pta4/kbd4 ?pta0/kbd0 ) . . . . . . . . . . . . . . . . 24 1.5.7 port b i/o pins (ptb7/ad7/tbch1, ptb6/ad6/tbch0, ptb5/ad5?ptb0/ad0) . . . . . . . 24 1.5.8 port c i/o pins (ptc4/osc1, ptc3/osc2, ptc2/mclk, ptc1/mosi, ptc0/miso). . . . 24 1.5.9 port d i/o pins (ptd1/tach1?ptd0/tach0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.10 port e i/o pins (pte1/rxd?pte0/txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 random access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.1 flash control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.2 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.3 flash mass erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.4 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.5 flash block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.6 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.7 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
table of contents mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 8 freescale semiconductor chapter 3 analog-to-digital c onverter (adc) module 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.5 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.6 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.1 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.2 adc analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.3 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.5 adc voltage in (advin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.6 adc external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.6.1 v refh and v refl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6.6.2 anx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.6.6.3 grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7.2 adc data register high (adrh) and data register low (adrl) . . . . . . . . . . . . . . . . . . . 51 3.7.2.1 left justified mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.7.2.2 right justified mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.7.2.3 left justified signed data mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 3.7.2.4 eight bit truncation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.7.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 chapter 4 bemf counter module (bemf) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 bemf register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 9 chapter 5 configuration registers (config1 and config2) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 computer operating properly (cop) module 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.6 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.7 copd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.8 coprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.8 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 chapter 7 central processor unit (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
table of contents mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 10 freescale semiconductor chapter 8 internal clock gener ator (icg) module 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.1 clock enable circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.3.2 internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.3.2.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.2.2 modulo n divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.2.3 frequency comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.2.4 digital loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.3.3 external clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.3.3.1 external oscillator amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.3.3.2 external clock input path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.3.4 clock monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.3.4.1 clock monitor reference generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.3.4.2 internal clock activity detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.3.4.3 external clock activity detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.3.5 clock selection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.5.1 clock selection switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.5.2 clock switching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4 usage notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4.1 switching clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4.2 enabling the clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.4.3 using clock monitor interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.4.4 quantization error in dco output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.4.4.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.4.4.2 binary weighted divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.4.4.3 variable-delay ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.4.4.4 ring oscillator fine-adjust circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.4.5 switching internal clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.4.6 nominal frequency settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.4.6.1 settling to within 15 percent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.4.6.2 settling to within 5 percent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.4.6.3 total settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.4.7 trimming frequency on the internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.6 config options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.1 external clock enable (extclken) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.2 external crystal enable (extxtalen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.3 slow external clock (extslow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.4 oscillator enable in stop (oscenin stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 11 8.7 input/output (i/o) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.7.1 icg control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.7.2 icg multiplier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.7.3 icg trim register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.7.4 icg trim value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.7.5 icg dco divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.7.6 icg dco stage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 chapter 9 external interrupt (irq) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 9.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 chapter 10 keyboard interrup t (kbd) module 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.6 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.7.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.7.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 chapter 11 low-voltage inhibit (lvi) module 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.3.3 false reset protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.3.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
table of contents mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 12 freescale semiconductor chapter 12 input/output (i/o) ports (ports) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.5.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.6.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 chapter 13 enhanced serial communications interface (esci) module 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 0 13.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 13 13.6 esci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 37 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.7.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.7.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.8.1 esci control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.8.2 esci control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.8.3 esci control register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.8.4 esci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.8.5 esci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.8.6 esci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.8.7 esci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.9 esci arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.9.1 esci arbiter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.9.2 esci arbiter data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.9.3 bit time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.9.4 arbitration mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 chapter 14 system integrati on module (sim) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3.2.5 forced monitor mode entry reset (menrst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3.2.6 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 60 14.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 0 14.5 program exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
table of contents mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 14 freescale semiconductor 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 chapter 15 serial peripheral interface (spi) module 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3 pin name and register name conventi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.5 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.5.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 15.5.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.5.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.5.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.6.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.8 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.10 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.11 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.12.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.12.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.12.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.12.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.12.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.13 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.13.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.13.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.13.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 15 chapter 16 timebase module (tbm) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16.5 tbm interrupt rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.7 timebase control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 chapter 17 timer interface a (tima) module 17.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.3.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 17.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 17.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 97 17.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 17.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.6 tima during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.7.1 tima channel i/o pins (ptd0/tach0, ptd1/tach1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.8.1 tima status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.8.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.8.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.8.4 tima channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.8.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 chapter 18 timer interface b (timb) module 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
table of contents mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 16 freescale semiconductor 18.3.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 18.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 18.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 18.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 18.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 18.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 18.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 18.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 18.6 timb during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 18.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 18.7.1 timb channel i/o pins (ptb7/tbch1?ptb6/tbch0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 18.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.8.1 timb status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.8.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.8.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.8.4 timb channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 18.8.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 chapter 19 development support 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 19.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 19.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 19.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.2.1.3 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 27 19.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 19.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 19.2.2.3 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 19.2.2.4 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 19.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 19.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 19.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 19.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 19.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.6 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 19.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 17 chapter 20 electrical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 20.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 20.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 20.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 20.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 20.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 20.7 internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 20.8 external oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 20.9 trimmed accuracy of the internal clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 20.9.1 trimmed internal clock generator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 20.10 analog-to-digital converter (adc) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 20.11 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 20.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 chapter 21 ordering information and m echanical specifications 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 21.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 21.3 32-pin qfp (case number 873) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 appendix a mc68hc908ey8 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 a.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 a.3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 a.4 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 glossary glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 revision history revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
table of contents mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 18 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 19 chapter 1 general description 1.1 introduction the mc68hc908ey16 is a member of the low-co st, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. the information contained in this document pertains to the mc68hc908ey8 with the exceptions noted in appendix a mc68hc908ey8 . 1.2 features for convenience, features have been organized to reflect: standard features of the mc68hc908ey16 features of the cpu08 standard features of the mc68hc908ey16 include: high-performance m68hc08 architecture optimized for c-compilers fully upward-compatible object code wi th m6805, m146805, and m68hc05 families 8-mhz internal bus frequency at 5v internal oscillator requiring no external components: ? software selectable bus frequencies ? 25 percent accuracy with a trimming capability of better than 1 percent ? clock monitor ? option to allow use of external clock s ource or external crystal/ceramic resonator 15,872 bytes of on-chip flash memo ry with in-circuit programming flash program memory security (1) 512 bytes of on-chip random-access memory (ram) low voltage inhibit (lvi) module internal clock generator module (icg) two 16-bit, 2-channel timer (tima and timb) interface modules with selectable input capture, output compare, and pulse-width mo dulation (pwm) capability on each channel 8-channel, 10-bit successive approximat ion analog-to-digital converter (adc) enhanced serial communications interface module (esci) for local interconnect network (lin) connectivity serial peripheral interface (spi) 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
general description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 20 freescale semiconductor timebase module (tbm) 5-bit keyboard interrupt (kbi) with wakeup feature 24 general-purpose input/output (i/o) pins external asynchronous interrupt pin with internal pullup (irq ) system protection features: ? optional computer operating properly (cop) reset ? illegal opcode detection with reset ? illegal address detection with reset 32-pin quad flat pack (qfp) package low-power design; fully static with stop and wait modes internal pullups on irq and rst to reduce customer system cost standard low-power modes of operation: ? wait mode ? stop mode master reset pin (rst ) and power-on reset (por) break module (brk) to allow single brea kpoint setting during in-circuit debugging higher current source capability on nine port lines for led drive (pta6/ss , pta5/spsck, pta4/kbd4 , pta3/kbd3 , pta2/kbd2 , pta1/kbd1 , pta0/kbd0 , ptc1/mosi, and ptc0/miso) features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16 8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support
mcu block diagram mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 21 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908ey16. figure 1-1. mcu block diagram single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
general description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 22 freescale semiconductor 1.4 pin assignments figure 1-2 shows the pin assignments for the mc68hc908ey16. figure 1-2. pin assignments 1.5 pin functions descriptions of the pin functions are provided here. 1.5.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-3 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. ptc2/mclk v refl ptc3/osc2 ptc4/osc1 ptb6/ad6/tbch0 ptb7/ad7/tbch1 pta0/kbd0 pta1/kbd1 pta2/kbd2 pte1/rxd pte0/txd ptc0/miso ptc1/mosi pta5/spsck pta6/ss ptb0/ad0 irq pta3/kbd3 pta4/kbd4 v refh v dda v dd v ss v ssa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 ptd1/tach1 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 rst ptb1/ad1 ptd0/tach0
pin functions mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 23 figure 1-3. power supply bypassing 1.5.2 oscillator pins (ptc4/osc1 and ptc3/osc2) the osc1 and osc2 pins are available through progr amming options in the configuration register. these pins then become the connections to an external clock source or crystal/ceramic resonator. when selecting ptc4 and ptc3 as i/o, osc1 and osc2 functions are not available. 1.5.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pullup resistor that is always activa ted, even when the reset pin is pulled low. see chapter 14 system integration module (sim) . 1.5.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. this pi n contains an internal pullup resistor that is always activated, even when the irq pin is pulled low. see chapter 9 external interrupt (irq) . 1.5.5 analog power su pply/reference pins (v dda , v refh , v ssa and v refl ) v dda and v ssa are the power supply pins for the analog-to-d igital converter (adc). decoupling of these pins should be as per the digital supply. note v refh is the high reference supply for the adc. v dda should be tied to the same potential as v dd via separate traces. v refl is the low reference supply for the adc. v ssa should be tied to the same potential as v ss via separate traces. see chapter 3 analog-to-digita l converter (adc) module . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications.
general description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 24 freescale semiconductor 1.5.6 port a i/o pins (pta6/ss , pta5/spsck, pta4/kbd4 ?pta0/kbd0 ) port a input/output (i/o) pins (pta6/ss , pta5/spsck, pta4/kbd4 , pta3/kbd3 , pta2/kbd2 , pta1/kbd1 , and pta0/kbd0 ) are special-function, bidirectional i/o port pins. pta5 and pta6 are shared with the serial peripheral interface (spi). pta4-pta0 can be programmed to serve as keyboard interrupt pins. see chapter 12 input/output (i/o) ports (ports) and chapter 9 external interrupt (irq) . 1.5.7 port b i/o pins (p tb7/ad7/tbch1, ptb6/ad6/t bch0, ptb5/ad5?ptb0/ad0) ptb7/ad7/tbch1, ptb6/ad6/tbch0, and ptb5/ad5?ptb 0/ad0 are special-function, bidirectional i/o port pins that can also be used for adc inputs. ptb7/ad7/tbch1 and ptb6/ad6/tbch0 are special function bidirectional i/o port pins that can also be used for timer interface pins. see and chapter 3 analog-to-digital converter (adc) module and chapter 17 timer interface a (tima) module . 1.5.8 port c i/o pins (ptc 4/osc1, ptc3/osc2, ptc2/mcl k, ptc1/mosi, ptc0/miso) ptc4/osc1?ptc0/miso are special-functi on, bidirectional i/o port pins. see chapter 12 input/output (i/o) ports (ports) . ptc3/osc2 and ptc4/osc1 are shared with the on-chip oscillator circuit through configuration options. see chapter 8 internal clock generator (icg) module . when applications require: ptc3/osc2 can be programmed to be osc2 ptc4/osc1 can be programmed to be osc1 ptc2/mclk is software selectable to be mclk, or bus clock out. ptc1/mosi can be programmed to be the mosi signal for the spi. ptc0/miso can be programmed to be the miso signal for the spi. 1.5.9 port d i/o pins (ptd1/tach1?ptd0/tach0) ptd1/tach1?ptd0/tach0 are special-function, bidirect ional i/o port pins that can also be programmed to be timer pins. see chapter 17 timer interface a (tima) module and chapter 12 input/output (i/o) ports (ports) . 1.5.10 port e i/o pi ns (pte1/rxd?pte0/txd) pte1/rxd?pte0/txd are special-function, bidirectiona l i/o port pins that can also be programmed to be enhanced serial communication interface (esci) pins. see chapter 13 enhanced serial communications interface (esci) module and chapter 12 input/output (i/o) ports (ports) . note any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc908ey16 do not require termination, termination is recommended to reduce the possibility of electro-static discharge damage.
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 25 chapter 2 memory 2.1 introduction the m68hc08 central processor unit (cpu08) can a ddress 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 16 kbytes of flash memory, 15, 872 bytes of user space 512 bytes of random-access memory (ram) 36 bytes of user-defined vectors 310 bytes of monitor routines in read-only memory (rom) 1024 bytes of integrated flash burn-in routines in rom 2.2 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable e ffects on microcontroller unit (mcu) operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2.4 input/output (i/o) section most of the control, status, and data registers ar e in the zero page area of $0000?$003f. additional i/o registers have these addresses: $fe00; sim break status register, sbsr $fe01; sim reset status register, srsr $fe03; sim break flag control register, sbfcr $fe08; flash control register, flcr $fe09; break address register high, brkh $fe0a; break address register low, brkl $fe0b; break status and control register, brkscr $fe0c; lvi status register, lvisr $ff7e; flash block protect register, flbpr $ff80; icg trim value (optional), icgt data registers are shown in figure 2-2 . and table 2-1 is a list of vector locations.
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 26 freescale semiconductor $0000 i/o registers 64 bytes $fe09 break address register high (brkh) $fe0a break address register low (brkl) $003f $fe0b break status and control register (brkscr) $0040 ram 512 bytes $fe0c lvi status register (lvisr) $fe0d reserved 3 bytes $023f $0240 unimplemented 3520 bytes $fe0f $fe10 reserved 16 bytes reserved for compatibility with monitor code for a-family parts $0fff $1000 reserved for integrated flash burn-in routines 1024 bytes $fe1f $fe20 monitor rom 310 bytes $13ff $1400 unimplemented 44,032 bytes ff55 ff56 unimplemented 40 bytes $bfff $c000 flash memory 15,872 bytes ff7d $ff7e flash block protect register (flbpr) $fdff $ff80 icg trim value (optional) (icgt) $fe00 sim break status register (sbsr) $ff7f unimplemented 93 bytes $fe01 sim reset status register (srsr) $fe02 reserved $ffdb $fe03 sim break flag control register (sbfcr) $ffdc flash vectors 36 bytes $fe04 reserved $fe05 reserved $ffff $fe06 reserved note: locations $fff6?$fffd are reserved for eight security bytes. $fe07 reserved for flash test control register (fltcr) $fe08 flash control register (flcr) figure 2-1. memory map
input/output (i/o) section mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 27 addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 115. read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 117. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 119. read:000 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 120. read:0000 0 0 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 115. read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0000 0 000 $0005 data direction register b (ddrb) see page 118. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:0000 0 000 $0006 data direction register c (ddrc) see page 119. read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:0000 0 000 $0007 data direction register d (ddrd) see page 121. read:0000 0 0 ddrd1 ddrd0 write: reset:0000 0 000 $0008 port e data register (pte) see page 122. read:0000 0 0 pte1 pte0 write: reset: unaffected by reset $0009 reserved r r r r r r r r $000a data direction register e (ddre) see page 123. read:0000 0 0 ddre1 ddre0 write: reset:0000 0 000 $000b bemf register (bemf) see page 55. read: bemf7 bemf6 bemf5 bemf4 bemf3 bemf2 bemf1 bemf0 write: reset:0000 0 000 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 7)
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 28 freescale semiconductor $000c reserved r r r r r r r r $000d spi control register (spcr) see page 184. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:0010 1 000 $000e spi status and control register (spscr) see page 186. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:0000 1 000 $000f spi data register (spdr) see page 188. read:r7r6r5r4 r3 r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset $0010 esci control register 1 (scc1) see page 138. read: loops ensci txinv m wake ilty pen pty write: reset:0000 0 000 $0011 esci control register 2 (scc2) see page 140. read: sctie tcie scrie ilie te re rwu sbk write: reset:0000 0 000 $0012 esci control register 3 (scc3) see page 142. read: r8 t8 r r orie neie feie peie write: reset:u000 0 000 $0013 esci status register 1 (scs1) see page 143. read: scte tc scrf idle or nf fe pe write: reset:1100 0 000 $0014 esci status register 2 (scs2) see page 145. read: 0 0 0 0 0 0 bkf rpf write: reset:0000 0 000 $0015 esci data register (scdr) see page 146. read:r7r6r5r4 r3 r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0016 esci baud rate register (scbr) see page 146. read: r linr scp1 scp0 r scr2 scr1 scr0 write: reset:0000 0 000 $0017 esci prescale register (scpsc) see page 147. read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:0000 0 000 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 7)
input/output (i/o) section mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 29 $0018 escii arbiter control register (sciactl) see page 151. read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:0000 0 000 $0019 esci arbiter data register (sciactl) see page 152. read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:0000 0 000 $001a keyboard status and control register (intkbscr) see page 109. read:0000keyf0 imaskk modek write: ackk reset:0000 0 000 $001b keyboard interrupt enable register (intkbier) see page 110. read:000 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:0000 0 000 $001c timebase control register (tbcr) see page 192. read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:0000 0 000 $001d irq status and control register (intscr) see page 104. read:0000irqf0 imask mode write: ack reset:0000 0 000 $001e configuration register 2 (config2) see page 57. read: r esci bdsrc ext- xtalen ext- slow ext- clken tmb- clksel oscenin- stop ssb- puenb write: reset:0000 0 001 $001f configuration register 1 (config1) see page 58. read: coprs lvistop lvirstd lvipwrd lvi5or3 (1) ssrec stop copd write: reset:0000 0 000 1. the lvi5or3 bit is cleared only by a power-on reset (por). $0020 timer a status and control register (tasc) see page 201. read: tof toie tstop 0 r ps2 ps1 ps0 write: 0 trst reset:0010 0 000 $0021 timer a counter register high (tacnth) see page 203. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:0000 0 000 $0022 timer a counter register low (tacntl) see page 203. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:0000 0 000 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 7)
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 30 freescale semiconductor $0023 timer a counter modulo register high (tamodh) see page 203. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:1111 1 111 $0024 timer a counter modulo register low (tamodl) see page 203. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:1111 1 111 $0025 timer a channel 0 status and control register (tasc0) see page 204. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:0000 0 000 $0026 timer a channel 0 register high (tach0h) see page 207. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0027 timer a channel 0 register low (tach0l) see page 207. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0028 timer a channel 1 status and control register (tasc1) see page 207. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:0000 0 000 $0029 timer a channel 1 register high (tach1h) see page 207. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a timer a channel 1 register low (tach1l) see page 207. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $002b timer b status and control register (tbsc) see page 217. read: tof toie tstop 0 r ps2 ps1 ps0 write: 0 trst reset:0010 0 000 $002c timer b counter register high (tbcnth) see page 219. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:0000 0 000 $002d timer b counter register low (tbcntl) see page 219. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:0000 0 000 $002e timer b counter modulo register high (tbmodh) see page 219. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:1111 1 111 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 7)
input/output (i/o) section mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 31 $002f timer b counter modulo register low (tbmodl) see page 219. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:1111 1 111 $0030 timer b channel 0 status and control register (tbsc0) see page 220. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:0000 0 000 $0031 timer b channel 0 register high (tbch0h) see page 223. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0032 timer b channel 0 register low (tbch0l) see page 223. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0033 timer b channel 1 status and control register (tbsc1) see page 220. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:0000 0 000 $0034 timer b channel 1 register high (tbch1h) see page 223. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0035 timer b channel 1 register low (tbch1l) see page 223. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0036 icg control register (icgcr) see page 97. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 reset:0000 1 000 $0037 icg multiplier register (icgmr) see page 98. read: n6 n5 n4 n3 n2 n1 n0 write: reset:0001 0 101 $0038 icg trim register (icgtr) see page 99. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:1000 0 000 $0039 icg divider control register (icgdvr) see page 99. read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000uuuu $003a icg dco stage control register (icgdsr) see page 100. read: dstg7 dstg6 dstg5 dstg4 ddstg3 dstg2 dstg1 dstg0 write:rrrr r rrr reset:uuuu u uuu addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 7)
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 32 freescale semiconductor $003b reserved r r r r r r r r $003c analog-to-digital status and control register (adscr) see page 49. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:0001 1 111 $003d analog-to-digital data register high (adrh) see page 51. read:0000 0 0ad9ad8 write: reset: unaffected by reset $003e analog-to-digital data register low (adrl) see page 53. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected by reset $003f analog-to-digital clock register (adclk) see page 53. read: adiv2 adiv1 adiv0 adiclk mode1 mode0 r 0 write: reset:0000 0 100 $fe00 sim break status register (sbsr) see page 166. read: rrrr r r sbsw r write: note reset:0000 0 000 note: writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 167. read: por pin cop ilop ilad menrst lvi 0 write: por:1000 0 000 $fe02 reserved $fe03 sim break flag control register (sbfcr) bcferrr r rrr $fe04 reserved $fe07 reserved $fe08 flash control register (flcr) see page 36. read:0000 hven mass erase pgm write: reset:0000 0 000 $fe09 break address register high (brkh) see page 228. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:0000 0 000 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 6 of 7)
input/output (i/o) section mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 33 $fe0a break address register low (brkl) see page 228. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:0000 0 000 $fe0b break status and control register (bscr) see page 228. read: brke brka 00 0 000 write: reset:0000 0 000 $fe0c lvi status register (lvisr) see page 112. read:lviout000 0 000 write: reset:0000 0 000 $ff7e flash block protect register (flbpr) (1) see page 99. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset $ff7f reserved $ff80 icg trim value (icgt) (2) see page 41. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset 1. non-volatile flash register. $ffff cop control register (copctl) see page 63. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 7 of 7)
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 34 freescale semiconductor table 2-1. vector addresses vector priority vector address vector lowest if16 $ffdc timebase interrupt vector (high) $ffdd timebase interrupt vector (low) if15 $ffde spi transmit vector (high) $ffdf spi transmit vector (low) if14 $ffe0 spi receive vector (high) $ffe1 spi receive vector (low) if13 $ffe2 adc conversion complete vector (high) $ffe3 adc conversion complete vector (low) if12 $ffe4 keyboard vector (high) $ffe5 keyboard vector (low) if11 $ffe6 esci transmit vector (high) $ffe7 esci transmit vector (low) if10 $ffe8 esci receive vector (high) $ffe9 esci receive vector (low) if9 $ffea esci error vector (high) $ffeb esci error vector (low) if8 $ffec timb overflow vector (high) $ffed timb overflow vector (low) if7 $ffee timb channel 1 vector (high) $ffef timb channel 1 vector (low) if6 $fff0 timb channel 0 vector (high) $fff1 timb channel 0 vector (low) if5 $fff2 tima overflow vector (high) $fff3 tima overflow vector (low) if4 $fff4 tima channel 1 vector (high) $fff5 tima channel 1 vector (low) if3 $fff6 tima channel 0 vector (high) $fff7 tima channel 0 vector (low) if2 $fff8 cmireq (high) $fff9 cmireq (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low)
random access memory (ram) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 35 2.5 random access memory (ram) addresses $0040?$00ff and $0100?$023f are ram locations. the location of the stack ram is programmable with the reset stack pointer instructio n (rsp). the 16-bit stack pointer allows the stack ram to be anywhere in the 64k-byte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 192 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for input/output (i/o ) control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access all page zero ram locations efficiently. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the central processor unit (cpu) registers. note for m6805, m146805, and m68hc05 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or dur ing the interrupt stacking operation. 2.6 flash memory (flash) the flash memory is an array of 15,872 bytes with an additional 36 bytes of user vectors and one byte used for block protection. note an erased bit reads as 1 and a programmed bit reads as 0. the program and erase operations are facilitated thr ough control bits in the flash control register (flcr). see 2.6.1 flash control register . the flash is organized internally as an 16,384-word by 8-bit complementary metal-oxide semiconductor (cmos) page erase, byte (8-bit) program embedded flash memory. each page consists of 64 bytes. the page erase operation erases all words within a page. a page is composed of two adjacent rows. a security feature prevents viewing of the flash contents. (1) in the 125c to 135c temperature range, the flash is guaranteed as read only. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 36 freescale semiconductor 2.6.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can be set only if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the 16-kbyte flash array for mass or page erase operation. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr)
flash memory (flash) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 37 2.6.2 flash page erase operation use this step-by-step procedure to erase a page (64 bytes) of flash memory to read as logic 1: 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note while these operations must be performed in the order shown, other unrelated operations may occur between the steps. note due to the security feature (see 19.3 monitor module (mon) ) the last page of the flash (0xffdc?0xffff), whic h contains the security bytes, cannot be erased by page erase operation. it can only be erased with the mass erase operation. in applications that require more than 1000 program /erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 38 freescale semiconductor 2.6.3 flash m ass erase operation use this step-by-step procedure to erase entire flash memory to read as logic 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. note mass erase is disabled whenever any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 1. when in monitor mode, with security sequence failed (see 19.3.2 security ), write to the flash block protect register in- stead of any flash address.
flash memory (flash) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 39 2.6.4 flash progra m/read operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $ xx60, $xx80, $xxa0, $xxc0, and $xxe0. use this step-by-step procedure to program a row of flash memory ( figure 2-4 is a flowchart representation). note to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read from the flash block protect register. 3. write any data to any flash address within the row address range desired. 4. wait for a time, t nvs (minimum of 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum of 5 s). 7. write data to the flash address (1) to be programmed. 8. wait for a time, t prog (minimum of 30 s). 9. repeat steps 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit. (1) 11. wait for a time, t nvh (minimum of 5 s). 12. clear the hven bit. 13. after a time, t rcv (minimum of 1 s), the memory can be accessed in read mode again. this program sequence is repeated throughout the memory until all data is programmed. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. 1. the time between each flash address change, or the time between the last flash address programmed to clearing the pgm bit, must not exceed the maximum programming time, t prog maximum.
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 40 freescale semiconductor figure 2-4. flash programming flowchart set hven bit read the flash block write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv yes no end of programming the time between each flash address change (step 7 to step 7), must not exceed the maximum programming time, t prog maximum. or the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) notes: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. protect register write data to the flash address to be programmed completed programming this row?
flash memory (flash) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 41 2.6.5 flash bl ock protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting a bloc k of memory from unintentional erase or program operations due to system malfunction. this protection is done by using the flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note in performing a program or erase operation, flbpr must be read after setting the pgm or erase bit and before asserting the hven bit. when flbpr is programmed with all 0s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory address ranges as shown in 2.6.6 flash block protect register . once the flbpr is programmed with a value other than $ff or $fe, any erase or program of the flbpr or the protected block of flash memory is prohibited. mass erase is disabled whenever any block is protected (flbpr does not equal $ff). the presence of a v tst on the irq pin will bypass the block protection so that all of the memory included in the block protect register is open for program and erase operations. 2.6.6 flash bloc k protect register the flash block protect register (flbpr) is impl emented as a byte within the flash memory, and therefore can be written only during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr7?bpr0 ? flash block protect bits these eight bits represent bits [13:6] of a 16-bit memory address. bit 15 and bit 14 are 1s and bits [5:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this star t address to the end of flash memory, at $ffff. with this mechanism, the protec t start address can be $xx00, $xx40, $xx80, and $xxc0 (64 bytes page boundaries) within the flash memory. figure 2-6. flash block protect start address address: $ff7e bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset. initial value from factory is $ff. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) 1 flbpr value 16-bit memory address 000000 start address of flash 1 block protect
memory mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 42 freescale semiconductor 2.6.7 wait mode putting the microcontroller unit (mcu) into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory ac tivity since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode. 2.6.8 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode. note standby mode is the power-saving mode of the flash module in which all internal control signals to the flash are inactive and the current consumption of the flash is at a minimum. table 2-2. examples of protect address ranges bpr[7:0] addresses of protect range $00 the entire flash memory is protected. $01 ( 0000 0001 )$c040 (11 00 0000 01 00 0000) ? $ffff $02 ( 0000 0010 )$c080 (11 00 0000 10 00 0000) ? $ffff $03 ( 0000 0011 ) $c0c0 (11 00 0000 11 00 0000) ? $ffff $04 ( 0000 0100 )$c100 (11 00 0001 00 00 0000) ? $ffff and so on... $fc ( 1111 1100 ) $ff00 (11 11 1111 00 00 0000) ? ffff $fd ( 1111 1101 ) $ff40 (11 11 1111 01 00 0000) ? $ffff flbpr and vectors are protected $fe ( 1111 1110 ) $ff80 (11 11 1111 10 00 0000) ? ffff vectors are protected $ff the entire flash memory is not protected.
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 43 chapter 3 analog-to-digital converter (adc) module 3.1 introduction this section describes the 10-bit analog-to-digital converter (adc). for further information regarding analog-to-digital converters on freescale microcontrollers, please consult the hc08 adc re ference manual, adcrm/ad. 3.2 features features of the adc module include: 8 channels with multiplexed input linear successive approximation 10-bit resolution, 8-bit accuracy single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock left or right justified result left justified sign data mode high impedance buffered adc input 3.3 functional description eight adc channels are available for sampling external sources at pins ptb7:ptb0. to achieve the best possible accuracy, these pins are im plemented as input-only pins when the analog-to-digital (a/d) feature is enabled. an analog multiplexer allows the single adc to select one of the 8 adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximation algorithm. when the conversion is completed, the adc places the result in the adc data register (adrh and adrl) and sets a flag or generates an interrupt. see figure 3-2 .
analog-to-digital co nverter (adc) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 44 freescale semiconductor figure 3-1. block diagram highlighting adc block and pins single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 45 figure 3-2. adc block diagram 3.3.1 adc port i/o pins ptb7:ptb0 are general-purpose i/o pins t hat are shared with the adc channels. see chapter 12 input/output (i/o) ports (ports) . the channel select bits define which adc channel/p ort pin will be used as the input signal. the adc overrides the port logic when that port is selected by the adc multiplexer. the remaining adc channels/port pins are controlled by the port logi c and can be used as general-purpose input/output (i/o) pins. writes to the port register or ddr will not have any effect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0. 3.3.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. all other input voltages will result in $3ff if greater than v refh and $000 if less than v refl . note input voltage should not exceed the analog supply voltages. see 20.10 analog-to-digital converter (adc) characteristics . internal data bus read ptb ptb interrupt logic channel select adc clock generator conversion complete adc voltage in advin adc clock cgmxclk bus clock adch[4:0] adc data registers adiv[2:0] adiclk aien coco/idmas disable adc channel x ptx
analog-to-digital co nverter (adc) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 46 freescale semiconductor 3.3.3 conversion time conversion starts after a write to the adscr. a conversion is between 16 and 17 adc clock cycles, therefore: the adc conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is either the bus cl ock or cgmxclk and is selectable by adiclk located in the adc clock register. for example, if cgmxclk is 4 mhz and is selected as the adc input clock source, the adc input clock divide-by-2 pr escale is selected and the bus frequency is 8 mhz: the adc frequency must be between f adic minimum and f adic maximum to meet a/d spec ifications. see 20.10 analog-to-digital converter (adc) characteristics . since an adc cycle may be comprised of several bus cy cles (four in the previous example) and the start of a conversion is initiated by a bus cycle write to th e adscr, from zero to four additional bus cycles may occur before the start of the initial adc cycle. this results in a fractional adc cycle and is represented as the 17th cycle. 3.3.4 continuous conversion in continuous conversion mode, the adc data regist ers adrh and adrl will be filled with new data after each conversion. data from the pr evious conversion will be overwri tten whether that data has been read or not. conversions will continue unt il the adco bit is cleared. the coco bit is set after the first conversion and will stay set for the next several conv ersions until the next write of the adc status and control register or the next read of the adc data register. 3.3.5 result justification the conversion result may be formatted in four different ways: 1. left justified 2. right justified 3. left justified sign data mode 4. 8-bit truncation mode all four of these modes are controlled using mode0 and mode1 bits located in the adc clock register (adclk). left justification will place the eight most signific ant bits (msb) in the corresponding adc data register high, adrh. this may be useful if the result is to be treated as an 8-bit result where the two least significant bits (lsb), located in the adc data regist er low, adrl, can be ignored. however, adrl must be read after adrh or else the interlocking wi ll prevent all new conversions from being stored. 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conversion time x bus frequency 16 to17 adc cycles conversion time = 4 mhz/2 number of bus cycles = (8 to 8.5 s) x 8 mhz = 64 to 68 cycles = 8 to 8.5 s
interrupts mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 47 right justification will place only the two msbs in the corresponding adc data register high, adrh, and the eight lsbs in adc data register low, adrl. this mode of operation typically is used when a 10-bit unsigned result is desired. left justified sign data mode is similar to left just ified mode with one exception. the msb of the 10-bit result, ad9 located in adrh, is complemented. th is mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. finally, 8-bit truncation mode will place the eight msbs in adc data register low, adrl. the two lsbs are dropped. this mode of operation is used when compatibility with 8-bit adc designs are required. no interlocking between adrh and adrl is present. note quantization error is affected when only the most significant eight bits are used as a result. see figure 3-3 . figure 3-3. 8-bit truncation mode error 3.3.6 monotonicity the conversion process is monot onic and has no missing codes. 3.4 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. ideal 10-bit characteristic with quantization = 1/2 ideal 8-bit characteristic with quantization = 1/2 10-bit truncated to 8-bit result when truncation is used, error from ideal 8-bit = 3/8 lsb due to non-ideal quantization. 000 001 002 003 004 005 006 007 008 009 00a 00b 000 001 002 003 8-bit result 10-bit result i nput voltage represented as 10-bit input voltage represented as 8-bit 1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 1/2 2 1/2 1 1/2
analog-to-digital co nverter (adc) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 48 freescale semiconductor 3.5 wait mode the wait instruction can put the mcu in low power-consumption standby mode. the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch[4:0] in the adc status and control register before executing the wait instruction. 3.6 i/o signals the adc module has eight input signals. 3.6.1 adc analog power pin (v dda ) the adc analog portion uses v dda as its power pin. connect the v dda pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. note route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 3.6.2 adc analog ground pin (v ssa ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same voltage potential as v ss . 3.6.3 adc voltage reference pin (v refh ) v refh is the power supply for setting the reference voltage v refh . connect the v refh pin to the same voltage potential as v dda . there will be a finite current associated with v refh . see chapter 20 electrical specifications . note route v refh carefully for maximum nois e immunity and place bypass capacitors as close as possible to the package. 3.6.4 adc voltage reference low pin (v refl ) v refl is the lower reference supply for the adc. connect the v refl pin to the same voltage potential as v ssa . a finite current will be associated with v refl . see chapter 20 electrical specifications . 3.6.5 adc voltage in (advin) advin is the input voltage signal from one of the 8 adc channels to the adc module. 3.6.6 adc external connections this section describes the adc external connections: v refh and v refl , anx, and grounding.
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 49 3.6.6.1 v refh and v refl both ac and dc current are drawn through the v refh and v refl loop. the ac current is in the form of current spikes required to supply c harge to the capacitor array at each successive approximation step. the current flows through the internal resistor string. the best external component to meet both these current demands is a capacitor in the 0.01 f to 1 f range with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as close as possible to the package pins. resistance in the path is not recomm ended because the dc current will cause a voltage drop which could result in conversion errors. 3.6.6.2 anx empirical data shows that capacitors from the analog inputs to v refl improve adc performance. 0.01- f and 0.1- f capacitors with good high-frequency characteristics are sufficient. these capacitors must be placed as close as possi ble to the package pins. 3.6.6.3 grounding in cases where separate power supplies are used for analog and digital power, the ground connection between these supplies should be at the v ssa pin. this should be the only ground connection between these supplies if possible. the v ssa pin makes a good single point ground location. connect the v refl pin to the same potential as v ssa at the single point ground location. 3.7 i/o registers these i/o registers control and monitor operation of the adc: adc status and control register, adscr adc data registers, adrh and ardl adc clock register, adclk 3.7.1 adc status and control register this section describes the function of the adc status and control register (adscr). writing adscr aborts the current conversion and initiates a new conversion. coco ? conversions complete bit when aien bit is 0, the coco is a read-only bit which is set each time a conversion is completed except in the continuous c onversion mode where it is set after the first conversion. this bit is cleared whenever the adc status and control register is written or whenever the adc data register is read. if aien bit is 1, the coco is a read/write bit. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0)/cpu interrupt (aien = 1) address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 figure 3-4. adc status and control register (adscr)
analog-to-digital co nverter (adc) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 50 freescale semiconductor aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conver sion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5- bit field which is used to select one of 8 adc channels. the adc channels are detailed in table 3-1 . note take care to prevent switching noise from corrupting the analog signal when simultaneously using a port pin as both an analog and digital input. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not used. note recovery from the disabled state requi res one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes as specified in table 3-1 are used to verify the operation of the adc bot h in production test and for user applications. table 3-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0 00001 ptb1 00010 ptb2 00011 ptb3 00100 ptb4 00101 ptb5 00110 ptb6 00111 ptb7 01000 unused * to 11010 11011reserved ** 1 1 1 0 0 unused * 1 1 1 0 1 v refh 1 1 1 1 0 v refl 1 1 1 1 1 adc power off * if any unused channels are selected, the resulting adc conversion will be unknown. ** used for factory testing.
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 51 3.7.2 adc data register high (a drh) and data register low (adrl) 3.7.2.1 left justified mode in left justified mode the adrh register holds the eight msbs of the 10-bit result. the adrl register holds the two lsbs of the 10-bit result. all other bits read as 0. adrh and adrl ar e updated each time an adc single channel conversion completes. reading adrh latc hes the contents of adrl until adrl is read. until adrl is read, all s ubsequent results will be lost. 3.7.2.2 right justified mode in right justified mode the adrh regist er holds the two msbs of the 10-bit result. all other bits read as 0. the adrl register holds the eight lsbs of the 10-bit result. adrh and adrl are updated each time an adc single channel conversion comple tes. reading adrh latches the contents of adrl until adrl is read. until adrl is read, all subsequent adc results will be lost. address: $003d adrh bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset address: $003e adrl read:ad1ad0000000 write: reset: unaffected by reset = unimplemented figure 3-5. adc data register high (adrh) and low (adrl) address: $003d adrh bit 7654321bit 0 read:000000ad9ad8 write: reset: unaffected by reset address: $003e adrl read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected by reset = unimplemented figure 3-6. adc data register high (adrh) and low (adrl)
analog-to-digital co nverter (adc) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 52 freescale semiconductor 3.7.2.3 left justified signed data mode in left justified signed data mode the adrh register holds the eight msbs of the 10-bit result. the only difference from left justified mode is that the ad9 is complemented. the adrl register holds the two lsbs of the 10-bit result. all other bits read as 0. adrh and adrl are updated each time an adc single channel conversion completes. reading adrh latches the contents of adrl until adrl is read. until adrl is read, all subsequent results will be lost. 3.7.2.4 eight bit truncation mode in 8-bit truncation mode the adrl register holds the ei ght msbs of the 10-bit result. the adrh register is unused and reads as 0. the adrl register is updated each time an adc single channel conversion completes. in 8-bit mode, the adrl regi ster contains no interlocking with adrh. address: $003d adrh bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset address: $003e adrl read:ad1ad0000000 write: reset: unaffected by reset = unimplemented figure 3-7. adc data register high (adrh) and low (adrl) address: $003d adrh bit 7654321bit 0 read:00000000 write: reset: unaffected by reset address: $003e adrl read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write: reset: unaffected by reset = unimplemented figure 3-8. adc data register high (adrh) and low (adrl)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 53 3.7.3 adc clock register this register selects the clock frequency for the adc, selecting between modes of operation. adiv2:adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field which se lects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurations. adiclk ? adc input clock select bit adiclk selects either bus clock or cgmxclk as t he input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less t han 1 mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at f adic , correct operation can be guaranteed. see 20.10 analog-to-digital converter (adc) characteristics . 1 = internal bus clock 0 = external clock, cgmxclk mode1:mode0 ? modes of result justification bits mode1:mode0 selects among four modes of operation. the manner in which the adc conversion results will be placed in the adc data registers is controlled by these modes of operation. reset returns right-justified mode. 00 = 8-bit truncation mode 01 = right justified mode 10 = left justified mode 11 = left justified sign data mode address: $003f address: bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk mode1 mode0 r 0 write: reset:00000100 = unimplemented figure 3-9. adc clock register (adclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care cgmxclk or bus frequency f adic = adiv[2:0]
analog-to-digital co nverter (adc) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 54 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 55 chapter 4 bemf counter module (bemf) 4.1 introduction this section describes the bemf module. the bemf counter integrates over time, while the ptd0/tach0 pin is active. this function is useful fo r measuring recirculation currents in motors occurring on switching of inductive loads. bemf is the abbreviation for b ack e lectro m agnetic f orce. 4.2 functional description the 8-bit bemf counter runs at the internal bus frequency divided by 64. whenever ptd0/tach0 is a logic 1, the counter increments by 1 with each period. 4.3 bemf register the bemf register contains the eight read-only bits of the bemf counter, showing its actual value. a read access to the bemf register resets all counter bits to 0. 4.4 input signal port d shares the ptd0/tach0 pin with the bemf m odule. to measure an external signal with the bemf module, ptd0/tach0 must be configured as an input (ddrd0 = 0). 4.5 low power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 4.5.1 wait mode the bemf module remains active after execution of the wait instruction. in wait mode the bemf register is not accessible by the cpu. address: $000b bit 7654321bit 0 read: bemf7 bemf6 bemf5 bemf4 bemf3 bemf2 bemf1 bemf0 write: reset:00000000 = unimplemented figure 4-1. bemf register (bemf)
bemf counter module (bemf) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 56 freescale semiconductor 4.5.2 stop mode the bemf module is inactive after execution of the stop instruction. in stop mode the bemf register is not accessible by the cpu. figure 4-2. block diagram highlighting bemf block and pins single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 57 chapter 5 configuration registers (config1 and config2) 5.1 introduction this section describes the configuration registers, config1 and config2. the configuration registers control these options: stop mode recovery time, 32 cgmxclk cycles or 4096 cgmxclk cycles computer operating properly (cop) tim eout period, 262,128 or 8176 cgmxclk cycles stop instruction computer operating properly (cop) module low-voltage inhibit (lvi) module control and voltage trip point selection enable/disable the oscillator (osc) during stop mode external clock/crystal source control enhanced sci clock source selection 5.2 functional description the configuration registers are used in the initializa tion of various options and can be written once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu), it is recommended that these registers be written immediately after reset. the configuration registers are located at $001e and $001f. for compatibility, a write to a read-only memory (rom) version of the mcu at this location will have no effect. the configuration register may be read at anytime. note the config module is known as an mor (mask option register) on a rom device. on a rom device, the option s are fixed at the time of device fabrication and are neither writable nor changeable by the user. on a flash device, the config registers are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . address: $001e bit 7 6 5 4 3 2 1 bit 0 read: r escibdsrc extxtalen extslow extclken tmbclksel osceninstop ssbpuenb write: reset: 0 0 0 0 0 0 0 1 r= reserved figure 5-1. configuration register 2 (config2)
configuration registers (config1 and config2) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 58 freescale semiconductor escibdsrc ? esci baud rate clock source bit escibdsrc controls the clock source used for the esci. the setting of the bit affects the frequency at which the esci operates. 1 = internal data bus clock used as clock source for esci 0 = cgmxclk used as clock source for esci extxtalen ? external crystal enable bit extxtalen enables the external oscillator circuits to be configured for a crystal configuration where the ptc4/osc1 and ptc3/osc2 pins are the connections for an external crystal. note this bit does not function without setting the extclken bit also. clearing the extxtalen bit (default setting) a llows the ptc3/osc2 pin to function as a general-purpose i/o pin. refer to table 5-1 for configuration options for the external source. see chapter 8 internal clock generator (icg) module for a more detailed description of the external clock operation. extxtalen, when set, also configures the clock moni tor to expect an external clock source in the valid range of crystals (30 khz to 100 khz or 1 mhz to 8 mhz). when extxtalen is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 hz to 32 mhz). extxtalen, when set, also configures the external clock stabilization divider in the clock monitor for a 4096-cycle timeout to allow the proper stabilizati on time for a crystal. when extxtalen is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a startup time. 1 = allows ptc3/osc2 to be an external crystal connection. 0 = ptc3/osc2 functions as an i/o port pin (default). address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 (1) ssrec stop copd write: reset:00000000 1. the lvi5or3 bit is cleared only by a power-on reset (por). figure 5-2. configuration register 1 (config1) table 5-1. external clock option settings external clock configuration bits pin function description extclken extxtalen ptc4/osc1 ptc3/osc2 00 ptc4 ptc3 default setting ? external oscillator disabled 01 ptc4 ptc3 external oscillator disabled since extclken not set 10 osc1 ptc3 external oscillator configured for an external clock source input (square wave) on osc1 11 osc1 osc2 external oscillator configured for an external crystal configuration on osc1 and osc2. system will also operate with square-wave clock source in osc1.
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 59 extslow ? slow external crystal enable bit the extslow bit has two functions. it configures the icg module for a fast (1 mhz to 8 mhz) or slow (30 khz to 100 khz) speed crystal. the option also configures the clock monitor operation in the icg module to expect an external freq uency higher (307.2 khz to 32 mhz) or lower (60 hz to 307.2 khz) than the base frequency of the internal oscillator. see chapter 8 internal clock generator (icg) module . 1 = icg set for slow external crystal operation 0 = icg set for fast external crystal operation extclken ? external clock enable bit extclken enables an external clock source or crystal /ceramic resonator to be used as a clock input. setting this bit enables ptc4/osc1 pin to be a clock i nput pin. clearing this bi t (default setting) allows the ptc4/osc1 and ptc3/osc2 pins to function as general-purpose input/output (i/o) pins. refer to table 5-1 for configuration options for the external source. see chapter 8 internal clock generator (icg) module for a more detailed description of the external clock operation. 1 = allows ptc4/osc1 to be an external clock connection 0 = ptc4/osc1 and ptc3/osc2 func tion as i/o port pins (default). tmbclksel ? timebase clock select bit tmbclksel enables an enable the extra divide by 128 prescaler in the timebase module. setting this bit enables the extra prescaler and clear ing this bit disables it. refer to table 16-1 for timebase divider selection details. 1 = enables extra divide by 128 prescaler in timebase module. 0 = disables extra divide by 12 8 prescaler in timebase module. osceninstop ? oscillator enable in stop mode bit osceninstop, when set, will enable the internal clock generator module to continue to generate clocks (either internal, iclk, or external, eclk) in stop mode. see chapter 8 internal clock generator (icg) module . this function is used to keep the timebase running while the rest of the microcontroller stops. when clear, all clock generation will cease and both iclk and eclk will be forced low during stop mode. the default state for this option is clear, disabling the icg in stop mode. 1 = oscillator enabled to operate during stop mode 0 = oscillator disabled during stop mode (default) note this bit has the same functionality as the oscstopenb config bit in mc68hc908gp20 and mc68hc908gr8 parts. ssbpuenb ? ss pullup enable bit clearing ssbpuenb enables the ss pullup resistor. 1 = disables ss pullup resistor. 0 = enables ss pullup resistor. coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. see chapter 6 computer operating properly (cop) module . 1 = cop timeout period = 8176 cgmxclk cycles 0 = cop timeout period = 262,128 cgmxclk cycles lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvisto p bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode
configuration registers (config1 and config2) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 60 freescale semiconductor lvirstd ? lvi reset disable bit lvirstd disables the reset si gnal from the lvi module. see chapter 11 low-voltage inhibit (lvi) module . 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. see chapter 11 low-voltage inhibit (lvi) module . 1 = lvi module power disabled 0 = lvi module power enabled lvi5or3 ? lvi 5-v or 3-v operating mode bit lvi5or3 selects the voltage operating mode of the lvi module. see chapter 11 low-voltage inhibit (lvi) module . the voltage mode selected for the lvi will typically be 5 v. however, users may choose to operate the lvi in 3-v mode if desired. see chapter 20 electrical specifications for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode. 0 = lvi operates in 3-v mode. note the lvi5or3 bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclck cycles note exiting stop mode by an lvi reset will result in the long stop recovery. if the system clock source selected is the inte rnal oscillator or the external crystal and the osceninstop configuration bit is not set, the oscill ator will be disabled during stop mode. the short stop recovery does not provide enough time for osci llator stabilization and thus the ssrec bit should not be set. when using the lvi during normal operation but disabling during stop mode, the lvi will have an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 cgmxclk cycles) gives a delay longer than the lvi enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery configuration option, the 32-cgmxclk delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 6 computer operating properly (cop) module . 1 = cop module disabled 0 = cop module enabled
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 61 chapter 6 computer operating pr operly (cop) module 6.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by periodically clearing the cop counter. 6.2 functional description figure 6-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asyn chronous reset after 8176 or 262,128 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in the config-1. when coprs = 0, a 4.9152-mhz crystal gives a cop timeout period of 53.3 ms. writing any value to location $ffff before 1. see chapter 14 system integration module (sim) for more details. copctl write busclkx4 reset vector fetch sim reset circuit reset status register internal reset sources (1) sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter cop counter
computer operating properly (cop) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 62 freescale semiconductor an overflow occurs prevents a cop reset by cl earing the cop counter and stages 4?12 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq pin is held at v tst . during the break state, v tst on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cg mxclk frequency is equal to the crystal frequency. 6.3.2 stop instruction the stop instruction signal clears the cop prescaler. 6.3.3 copctl write writing any value to the cop control register (copctl) (see 6.4 cop control register ) clears the cop counter and clears stages 12 through 4 of the cop prescaler. reading the cop control register returns the reset vector. 6.3.4 powe r-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. 6.3.5 internal reset an internal reset clears the cop prescaler and the cop counter. 6.3.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 6.3.7 copd the copd signal reflects the state of the cop dis able bit (copd) in the configuration register. see chapter 5 configuration registers (config1 and config2) .
cop control register mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 63 6.3.8 coprs the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register. see chapter 5 configuration registers (config1 and config2) . 6.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate cpu interrupt requests. 6.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin or on the rst pin. 6.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.7.1 wait mode the cop remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 6.7.2 stop mode stop mode turns off the cgmxclk input to the co p and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the configuration register (con fig) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instru ction, disable the stop instruction by clearing the stop bit. 6.8 cop module during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl)
computer operating properly (cop) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 64 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 65 chapter 7 central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map.
central processor unit (cpu) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 66 freescale semiconductor figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 7.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70
cpu registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 67 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc)
central processor unit (cpu) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 68 freescale semiconductor v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr)
arithmetic/logic unit (alu) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 69 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
central processor unit (cpu) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 70 freescale semiconductor 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c
instruction set summary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 71 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 7-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 72 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
instruction set summary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 73 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 7-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 74 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
opcode map mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 75 7.8 opcode map see table 7-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 76 freescale semiconductor central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 77 chapter 8 internal clock generator (icg) module 8.1 introduction the internal clock generator (icg) module is used to create a stable clock source for the microcontroller without using any external components. the icg gener ates the oscillator output clock (cgmxclk), which is used by the computer operating properly (cop), low-voltage inhibit (lvi), and other modules. the icg also generates the clock generator output (cgmout), which is fed to the system integration module (sim) to create the bus clocks. the bus fr equency will be one-fourth the frequency of cgmxclk and one-half the frequency of cgmout. finally, the icg generates the timebase clock (tbmclk), which is used in the timebase module (tbm). 8.2 features the icg has these features: selectable external clock generator, either 1-pin ex ternal source or 2-pin crystal, multiplexed with port pins internal clock generator with programmable frequenc y output in integer multiples of a nominal frequency (307.2 khz 25 percent) internal oscillator trimmed accuracy of 3.5 percent bus clock software selectable from either inter nal or external clock (bus frequency range from 76.8 khz 25 percent to 9.75 mhz 25 percent in 76.8-khz increments) note for the mc68hc908ey16, do not exceed the maximum bus frequency of 8 mhz at 5.0 v. timebase clock automatically selected from exte rnal clock if external clock is available clock monitor for both internal and external clocks 8.3 functional description the icg, shown in figure 8-2 , contains these major submodules: clock enable circuit internal clock generator external clock generator clock monitor circuit clock selection circuit
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 78 freescale semiconductor figure 8-1. block diagram highlighting icg block and pins single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 79 figure 8-2. icg module block diagram internal to mcu external external clock generator extclken extxtalen ptc4 logic ptc3 logic ecgs osc1 ptc4 osc2 ptc3 internal clock generator osceninstop simoscen ibase icgs cmon clock monitor circuit eclk iclk clock selection circuit eoff ioff cgmxclk cs cgmout extslow clock/pin enable circuit icgon ecgon ecgen icgen dstg[7:0] tbmclk reset ddiv[3:0] ficgs name name name configuration register bit register bit module signal n[6:0} trim[7:0] name top level signal
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 80 freescale semiconductor 8.3.1 clock enable circuit the clock enable circuit is used to enable the internal clock (iclk) or external clock (eclk) and the port logic which is shared with the oscillator pins (o sc1 and osc2). the clock enable circuit generates an icg stop (icgstop) signal which stops all clocks (iclk, eclk, and the low-frequency base clock, ibase). icgstop is set and the icg is disabled in stop mode if the oscillator enable stop bit (osceninstop) in the configuration (config) regist er is clear. the icg clocks will be enabled in stop mode if osceninstop is high. the internal clock enable signal (icgen) turns on th e internal clock generator which generates iclk. icgen is set (active) whenever the icgon bit is set and the icgstop signal is clear. when icgen is clear, iclk and ibase are both low. the external clock enable signal (ecgen) turns on the external clock generator which generates eclk. ecgen is set (active) whenever the ecgon bit is set and the icgstop signal is clear. ecgon cannot be set unless the external clock enable (extclken) bi t in the config is set. when ecgen is clear, eclk is low. the port c4 enable signal (pc4en) turns on the port c4 logic. since port c4 is on the same pin as osc1, this signal is only active (set) when the external cl ock function is not desired. therefore, pc4en is clear when ecgon is set. pc4en is not gated with icgstop, which means that if the ecgon bit is set, the port c4 logic will remain disabled in stop mode. the port c3 enable signal (pc3en) turns on the port c3 logic. since port c3 is on the same pin as osc2, this signal is only active (set) wh en 2-pin oscillator function is not des ired. therefore, pc3en is clear when ecgon and the external crystal enable (extxtalen) bit in the config are both set. pc4en is not gated with icgstop, which means that if ecgon and extxtalen are set, the port c3 logic will remain disabled in stop mode. 8.3.2 internal clock generator the internal clock generator, shown in figure 8-3 , creates a low frequency base clock (ibase), which operates at a nominal frequency (f nom ) of 307.2 khz 25 percent, and an internal clock (iclk) which is an integer multiple of ibase. this multiple is the icg multiplier factor (n), which is programmed in the icg multiplier register (icgmr). the internal cl ock generator is turned of f and the output clocks (ibase and iclk) are held low when the internal clock generator enable signal (icgen) is clear. the internal clock generator contains: a digitally controlled oscillator a modulo n divider a frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators a digital loop filter
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 81 figure 8-3. internal clock generator block diagram 8.3.2.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccu rate oscillator which generates the internal clock (iclk). the clock period of iclk is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because of only a limited number of bits in ddiv and dstg, the precision of the output (iclk) is restricted to a precision of approximately 0.202 percent to 0.368 percent when measured over several cycles (of the desired frequency). additionally, since the propagat ion delays of the devices used in the dco ring oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require alternately running faster and slower than desir ed, making the worst case cycle-to-cycle frequency variation 6.45 percent to 11.8 percent (of the desired frequency). the valid values of ddiv:dstg range from $000 to $9ff. for more information on the quantization error in the dco, see 8.4.4 quantization error in dco output . 8.3.2.2 modulo n divider the modulo n divider creates the lo w-frequency base clock (i base) by dividing the internal clock (iclk) by the icg multiplier factor (n), contained in the ic g multiplier register (icgmr). when n is programmed to a $01 or $00, the divider is di sabled and iclk is passed through to ibase undivided. when the internal clock generator is stable, the frequency of ibase will be equal to the nominal frequency (f nom ) of 307.2 khz 25 percent. 8.3.2.3 frequency comparator the frequency comparator effectiv ely compares the low-frequency base clock (ibase) to a nominal frequency, f nom . first, the frequency comparator converts ibase to a voltage by charging a known capacitor with a current reference for a period dependent on ibase. this voltage is compared to a voltage digitally iclk trim[7:0] voltage and current references digital ++ + ? ? ? n[6:0] dstg[7:0] ficgs icgen ibase ddiv[3:0] loop filter controlled oscillator frequency comparator clock generator modulo n divider name name name configuration register bit register bit module signal name top level signal
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 82 freescale semiconductor reference with comparators, whose outputs are fed to the digital loop filter. the dependence of these outputs on the capacitor size, current reference, and voltage reference causes up to 25 percent error in f nom . 8.3.2.4 digital loop filter the digital loop filter (dlf) uses the outputs of the frequency comparator to adjust the internal clock (iclk) clock period. the dlf generates the dco divider control bits (ddiv[3:0]) and the dco stage control bits (dstg[7:0]), which are fed to t he dco. the dlf first concatenates the ddiv and dstg registers (ddiv[3:0]:dstg[7:0]) and then adds or subtracts a value dependent on the relative error in the low-frequency base clock?s period, as shown in table 8-1 . in some extreme error conditions, such as operating at a v dd level which is out of specification, the dlf may attempt to use a value above the maximum ($9ff) or below the minimum ($000). in both cases, the value for ddiv will be between $a and $f. in this range, the ddiv value will be interpret ed the same as $9 (the slowest condition). recovering from this condition requires subtracting (increasing frequency) in the normal fashion until the value is again below $9ff. (if the desired value is $9xx, the value may settle at $axx through $fxx. this is an acceptable operating condition.) if the error is less than 5 percent, the internal clock generator?s filter stable indicator (ficgs) is set, indicating rela tive frequency accuracy to the clock monitor. 8.3.3 external clock generator the icg also provides for an external oscillator or ex ternal clock source, if desired. the external clock generator, shown in figure 8-4 , contains an external oscillator amplifier and an external clock input path. table 8-1. correction sizes from dlf to dco frequency error of ibase compared to f nom ddvi[3:0]:dstg[7:0] correction current to new ddiv[3:0]:dstg[7:0] (1) 1. x = maximum error is independent of value in ddiv[3:0]. ddiv increments or decrements wh en an addition to dstg[7:0] carries or borrows. relative correction in dco ibase < 0.85 f nom ?32 (?$020) minimum $xff to $xdf ?2/31 ?6.45% maximum $x20 to $x00 ?2/19 ?10.5% 0.85 f nom < ibase ibase < 0.95 f nom ?8 (?$008) minimum $xff to $xf7 ?0.5/31 ?1.61% maximum $x08 to $x00 ?0.5/17.5 ?2.86% 0.95 f nom < ibase ibase < f nom ?1 (?$001) minimum $xff to $xfe ?0.0625/31 ?0.202% maximum $x01 to $x00 ?0.0625/17.0625 ?0.366% f nom < ibase ibase < 1.05 f nom +1 (+$001) minimum $xfe to $xff +0.0625/30.9375 +0.202% maximum $x00 to $x01 +0.0625/17 +0.368% 1.05 f nom < ibase ibase < 1.15 f nom +8 (+$008) minimum $xf7 to $xff +0.5/30.5 +1.64% maximum $x00 to $x08 +0.5/17 +2.94% 1.15 f nom < ibase +32 (+$020) minimum $xdf to $xff +2/29 +6.90% maximum $x00 to $x20 +2/17 +11.8%
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 83 8.3.3.1 external oscillator amplifier the external oscillator amplifier prov ides the gain required by an external crystal connected in a pierce oscillator configuration. the amount of this gain is controlled by the slow external (extslow) bit in the config. when extslow is set, the amplifier gain is reduced for operating low-frequency crystals (32 khz to 100 khz). when extslow is clear, the ampl ifier gain will be sufficient for 1-mhz to 8-mhz crystals. extslow must be configured correctly for the given crystal or the circuit may not operate. the amplifier is enabled when the external clock generator enable (ecgen) signal is set and when the external crystal enable (extxtalen) bit in the config is set. ecgen is controlled by the clock enable circuit (see 8.3.1 clock enable circuit ) and indicates that the external clock function is desired. when enabled, the amplifier will be connected between t he ptc4/osc1 and ptc3/osc2 pins. otherwise, the ptc3/osc2 pin reverts to its port function. figure 8-4. external clock generator block diagram in its typical configuration, the external oscillator requires five external components: 1. crystal, x 1 2. fixed capacitor, c 1 3. tuning capacitor, c 2 (can also be a fixed capacitor) 4. feedback resistor, rb 5. series resistor, r s (included in figure 8-4 to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information.) c 1 c 2 r b x 1 r s * ecgen extxtalen eclk internal to mcu external osc1 ptc4 osc2 ptc3 amplifier input path extslow name name name name configuration bit top level signal register bit module signal external clock generator these components are required for external crystal use only. *r s can be 0 (shorted) when used with higher- frequency crystals. refer to manufacturer?s data.
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 84 freescale semiconductor 8.3.3.2 external clock input path the external clock input path is the means by which the microcontroller uses an external clock source. the input to the path is the ptc4/osc1 pin and the ou tput is the external clock (eclk). the path, which contains input buffering, is enabled when the exter nal clock generator enable signal (ecgen) is set. when not enabled, the ptc4/osc1 pin reverts to its port function. 8.3.4 clock m onitor circuit the icg contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (eclk) and the internal clock (iclk) to dete rmine if either clock source has been corrupted. the clock monitor circuit, shown in figure 8-5 , contains these blocks: clock monitor reference generator internal clock activity detector external clock activity detector figure 8-5. clock monitor block diagram extxtalen extslow ficgs ioff cmon ficgs ibase icgen eref ioff icgs ibase extxtalen extslow ecgs eclk ecgen icgon eref estbclk iref estbclk iref ecgen eclk cmon ecgs eoff cmon eoff ecgs icgs ibase icgen eclk ecgen iclk activity detector reference generator eclk activity detector name name name configuration register bit register bit module signal name top level signal
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 85 8.3.4.1 clock monitor reference generator the clock monitor uses a reference based on one clock source to monitor the other clock source. the clock monitor reference generator generates the extern al reference clock (eref) based on the external clock (eclk) and the internal reference clock (iref) based on the internal clock (iclk). to simplify the circuit, the low-frequency base clock (ibase) is used in place of iclk bec ause it always operates at or near 307.2 khz. for proper operation, eref must be at least twice as slow as ibase and iref must be at least twice as slow as eclk. to guarantee that iref is slower than eclk and er ef is slower than ibase, one of the signals is divided down. which signal is divided and by how much is determined by the external slow (extslow) and external crystal enable (extxtalen) bits in the config, according to the rules in table 8-2 . note each signal (ibase and eclk) is always divided by four. a longer divider is used on either ibase or eclk based on the extslow bit. to conserve size, the long divider (divide by 4096) is al so used as an external cr ystal stabilization divider. the divider is reset when the external clock generator is turned off or in stop mode (ecgen is clear). when the external clock generator is first turned on, the external clock generator stable bit (ecgs) will be clear. this condition automatically selects eclk as the input to the long divider. the external stabilization clock (estbclk) will be eclk divided by 16 when extxtalen is low or 4096 when extxtalen is high. this timeout allows the crystal to stabilize. the falling edge of estbclk is used to set ecgs, which will set after a full 16 or 4096 cycles. when ecgs is set, the divider returns to its normal function. estbclk may be generated by either ibase or eclk, but any clocking will only reinforce the set condition. if ecgs is cleared because the clock monitor determined that eclk was inactive, the divider will revert to a stabilizati on divider. since this will change the er ef and iref divide ratios, it is important to turn the clock monitor off (cmon = 0) a fter inactivity is detected to ensure valid recovery. 8.3.4.2 internal clock activity detector the internal clock activity detector, shown in figure 8-6 , looks for at least one falling edge on the low-frequency base clock (ibase) every time the external reference (eref) is low. since eref is less than half the frequency of ibase, this should occur every time. if it does not occur two consecutive times, the internal clock inactivity indicator (ioff) is set. ioff will be cleared the next time there is a falling edge of ibase while eref is low. the internal clock stable bit (icgs) is also generated in the internal clock activi ty detector. icgs is set when the internal clock generator?s filter stable si gnal (ficgs) indicates that ibase is within about 5 percent of the target 307.2 khz 25 percent for two consecutive meas urements. icgs is cleared when ficgs is clear, the internal clock generator is turned off or is in stop mode (icgen is clear), or when ioff is set.
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 86 freescale semiconductor figure 8-6. internal clock activity detector 8.3.4.3 external clock activity detector the external clock activity detector, shown in figure 8-7 , looks for at least one falling edge on the external clock (eclk) every time the internal reference (iref) is low. since iref is less than half the frequency of eclk, this should occur every time. if it does not occur two consecutive times, the external clock inactivity indicator (eoff) is set. eo ff will be cleared the next time there is a falling edge of eclk while iref is low. the external clock stable bit (ecgs) is also generated in the external clock activity detector. ecgs is set on a falling edge of the external stabilization clock (estbclk). this will be 4096 eclk cycles after the external clock generator on bit is set, or the mcu exits stop mode (ecgen = 1) if the external crystal enable (extxtalen) in the config is set, or 16 cy cles when extxtalen is clear. ecgs is cleared when the external clock generator is turned off or in stop mode (ecgen is clear) or when eoff is set. figure 8-7. external clock activity detector icgs ioff ibase r dq ck dffrr r icgen r d ck dffrs s q ck q 1/4 r ficgs eref cmon r dq ck dffrr r name name name name configuration register bit top level signal register bit module signal dlf measure output clock eggs eoff eclk r d q ck dffrr r estbclk r d ck dffrs s q ck q 1/4 r ecgen iref cmon name name name name configuration register bit top level signal register bit module signal
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 87 8.3.5 clock se lection circuit the clock selection circuit, shown in figure 8-8 , contains two clock switches which generate the oscillator output clock (cgmxclk) and the timebase clock (tbmclk) from either the internal clock (iclk) or the external clock (eclk). the clock selection circuit also contains a divide-by-two circuit which creates the clock generator output clock (cgmout) , which generates the bus clocks. figure 8-8. clock selection circuit block diagram 8.3.5.1 clock selection switches the first switch creates the oscillator output clock (cgm xclk) from either the internal clock (iclk) or the external clock (eclk), based on the clock select bi t (cs; set selects eclk, clear selects iclk). when switching the cs bit, both iclk and eclk must be on (icgon and ecgon set). the clock being switched to also must be stable (icgs or ecgs set). the second switch creates the timebase clock (tbmclk) from iclk or eclk based on the external clock on bit. when ecgon is set, the switch automatically sele cts the external clock, regardless of the state of the ecgs bit. 8.3.5.2 clock switching circuit to robustly switch between the internal clock (iclk) and the external clock (eclk), the switch assumes the clocks are completely asynchr onous, so a synchronizing circuit is required to make the transition. when the select input (the clock select bit for the oscillator output clock switch or the external clock on bit for the timebase clock switch) is changed, the switch will continue to operate off the original clock for between one and two cycles as the select input is transitioned through one side of the synchronizer. next, the output will be held low for between one and two cycles of the new clock as the select input transitions through the other side. then the output starts swit ching at the new clock?s frequency. this transition guarantees that no glitches will be seen on the output even though the select input may change iclk eclk ioff eoff force_i force_e select output iclk eclk ioff eoff force_i force_e select output reset eclk eoff ecgon iclk ioff v ss cs div2 name name name name configuration register bit top level signal register bit module signal synchronizing clock switcher synchronizing clock switcher cgmout cgmxclk tbmclk
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 88 freescale semiconductor asynchronously to the clocks. the unpredictably of the transition period is a necessary result of the asynchronicity. the switch automatically selects iclk during reset. when the clock monitor is on (cmon is set) and it determines one of the clock sources is inactive (as indicated by the ioff or eoff signals), the circuit is forced to select the active clock. there are no clocks for the inactive side of the synchronizer to properly operate, so that side is forced deselected. however, the active side will not be selected until one to two clock cycles after the ioff or eoff signal transitions. 8.4 usage notes the icg has several features which can provide protec tion to the microcontroller if properly used. other features can greatly simplify usage of the icg if ce rtain techniques are employed. this section describes several possible ways to use the icg and its features. these techniques are not the only ways to use the icg and may not be optimum for all environments. in any case, these techniques should be used only as a template, and the user should modify them according to the application?s requirements. these notes include: switching clock sources enabling the clock monitor using clock monitor interrupts quantization error in digitally controlled oscillator (dco) output switching internal clock frequencies nominal frequency settling time improving frequency settling time trimming frequency 8.4.1 switchin g clock sources switching from one clock source to another requi res both clock sources to be enabled and stable. a simple flow requires: enable desired clock source wait for it to become stable switch clocks disable previous clock source the key point to remember in this flow is that th e clock source cannot be switched (cs cannot be written) unless the desired clock is on and stable. a short assemb ly code example of how to employ this flow is shown in figure 8-9 . this code is for illustrativ e purposes only and does not re present valid syntax for any particular assembler.
usage notes mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 89 ;clock switching code example ;this code switches from internal to external clock ;clock monitor and interrupts are not enabled start lda #$13 ;mask for cs, ecgon, ecgs ; if switching from external to internal, mask is $0c. loop ** ** ;other code here, such as writing the cop, since ecgs may ; take some time to set sta icgcr ;try to set cs, ecgon and clear icgon. icgon will not ; clear until cs is set, and cs will not set until ; ecgon and ecgs are set. cmpa icgcr ;check to see if ecgs set, then cs set, then icgon clear bne loop ;keep looping until icgon is clear. figure 8-9. code example for switching clock sources 8.4.2 enabling the clock monitor many applications require the clock monitor to dete rmine if one of the clock sources has become inactive, so the other can be used to recover from a poten tially dangerous situation. using the clock monitor requires both clocks to be active (ecgon and icgon both set). to enable the clock monitor, both clocks also must be stable (ecgs and icgs both set). this is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable. enabling the clock monitor and clock monitor in terrupts requires a flow similar to this: enable the alternate clock source wait for both clock sources to be stable switch to the desired clock source if necessary enable the clock monitor enable clock monitor interrupts these events must happen in sequence. a short assembly code example of how to employ this flow is shown in figure 8-10 . this code is for illustrative purposes on ly and does not represent valid syntax for any particular assembler. ;clock monitor enabling code example ;this code turns on both clocks, selects the desired ; one, then turns on the clock monitor and interrupts start lda #$af ;mask for cmie, cmon, icgon, icgs, ecgon, ecgs ; if internal clock desired, mask is $af ; if external clock desired, mask is $bf ; if interrupts not desired mask is $2f int; $3f ext loop ** ** ;other code here, such as writing the cop, since ecgs ; and icgs may take some time to set. sta icgcr ;try to set cmie. cmie wont set until cmon set; cmon ; won?t set until icgon, icgs, ecgon, ecgs set. brset 6,icgcr,error ;verify cmf is not set cmpa icgcr ;check if ecgs set, then cmon set, then cmie set bne loop ;keep looping until cmie is set. figure 8-10. code example for enabling the clock monitor
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 90 freescale semiconductor 8.4.3 using clock monitor interrupts the clock monitor circuit can be used to recover from pe rilous situations such as crystal loss. to use the clock monitor effectively, t hese points should be observed: enable the clock monitor and clock monitor interrupts. the first statement in the clock monitor interrupt service routine (cmisr) should be a read to the icg control register (icgcr) to verify that the cloc k monitor flag (cmf) is set. this is also the first step in clearing the cmf bit. the second statement in the cmisr should be a wr ite to the icgcr to clear the cmf bit (write the bit low). writing the bit high will not affect it. this statement does not n eed to immediately follow the first, but must be contained in the cmisr. the third statement in the cmisr should be to clear the cmon bit. this is required to ensure proper reconfiguration of the reference dividers. this statement also must be contained in the cmisr. although the clock monitor can be enabled only when bo th clocks are stable (icgs is set or ecgs is set), it will remain set if o ne of the clocks goes unstable. the clock monitor only works if the external sl ow (extslow) bit in the config is set to the correct value. the internal and external clocks must both be enabled and running to use the clock monitor. when the clock monitor detects inactivity, the inac tive clock is automatically deselected and the active clock selected as the source for cgmx clk and tbmclk. the cmisr can use the state of the cs bit to check which clock is inactive. when the clock monitor detects inactivity, t he application may have been subjected to extreme conditions which may have affected other circ uits. the cmisr should take any appropriate precautions. 8.4.4 quantization error in dco output the digitally controlled oscillator (dco) is comprised of three major sub-blocks: 1. binary weighted divider 2. variable-delay ring oscillator 3. ring oscillator fine-adjust circuit each of these blocks affects the clock period of the in ternal clock (iclk). since these blocks are controlled by the digital loop filter (dlf) outputs ddiv and dstg, the output of the dco can change only in quantized steps as the dlf increments or decrement s its output. the following sections describe how each block will affect the output frequency. 8.4.4.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccu rate oscillator which generates the internal clock (iclk), whose clock period is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because of the digital nature of the dco, the clock period of iclk will change in quantized steps. this will create a clock period difference or quantization e rror (q-err) from one cycle to the next. over several cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202 percent to 0.368 percent. the dependence of this error on the ddiv[3:0] value and the number of cycles the error is measured over is shown in table 8-2 .
usage notes mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 91 8.4.4.2 binary weighted divider the binary weighted divider divides the output of the ring oscillator by a power of two, specified by the dco divider control bits (ddiv[3:0]). ddiv maximizes at %1001 (values of %1010 through %1111 are interpreted as %1001), which corresponds to a divide by 512. when ddiv is %0000, the ring oscillator?s output is divided by 1. incrementing ddiv by one wi ll double the period; decrementing ddiv will halve the period. the dlf cannot directly increment or decrement ddiv; ddiv is only incremented or decremented when an addition or subtraction to dstg carries or borrows. 8.4.4.3 variable-delay ring oscillator the variable-delay ring oscill ator?s period is adjustable from 17 to 31 stage delays, in increments of two, based on the upper three dco stage control bits (dstg[7:5]). a dstg[7:5] of %000 corresponds to 17 stage delays; dstg[7:5] of %111 corresponds to 31 stage delays. adjusting the dstg[5] bit has a 6.45 percent to 11.8 percent effect on the output frequency. this also corresponds to the size correction made when the frequency error is greater than 15 percent. the value of the binary weighted divider does not affect the relative change in output clock period for a given change in dstg[7:5]. 8.4.4.4 ring oscillator fine-adjust circuit the ring oscillator fine-adjust ci rcuit causes the ring oscillator to effectively operate at non-integer numbers of stage delays by operating at two different points for a variable number of cycles specified by the lower five dco stage control bits (dstg[4:0]). for example: when dstg[7:5] is %011, the ring oscilla tor nominally operates at 23 stage delays. when dstg[4:0] is %00000, the ring will always operate at 23 stage delays. when dstg[4:0] is %00001, the ring will operate at 25 stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles. likewise, when dstg[4:0] is %11111, the ring oper ates at 25 stage delays for 31 of 32 cycles and at 23 stage delays for one of 32 cycles. table 8-2. quantization error in iclk ddiv[3:0] iclk cycles bus cycles iclk q-err %0000 (min) 1 na 6.45%?11.8% %0000 (min) 4 1 1.61%?2.94% %0000 (min) 32 8 0.202%?0.368% %0001 1 na 3.23%?5.88% %0001 4 1 0.806%?1.47% %0001 16 4 0.202%?0.368% %0010 1 na 1.61%?2.94% %0010 4 1 0.403%?0.735% %0010 8 2 0.202%?0.368% %0011 1 na 0.806%?1.47% %0011 4 1 0.202%?0.368% %0100 1 na 0.403%?0.735% %0100 2 1 0.202%?0.368% %0101?%1001 (max) 1 1 0.202%?0.368%
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 92 freescale semiconductor when dstg[7:5] is %111, similar results are achiev ed by including a variable divide-by-two, so the ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the remainder of the cycles. adjusting the dstg[0] bit has a 0.202 percent to 0.368 percent effect on the output clock period. this corresponds to the minimum size correction made by the dlf, and the inherent, long-term quantization error in the output frequency. 8.4.5 switching in ternal clock frequencies the frequency of the internal clock (iclk) may need to be changed for some applications. for example, if the reset condition does not provide the correct freq uency, or if the clock is slowed down for a low-power mode (or sped up after a low-power mode), the freq uency must be changed by programming the internal clock multiplier factor (n). the frequency of iclk is n times the frequency of ibase, which is 307.2 khz 25 percent. before switching frequencies by changing the n val ue, the clock monitor must be disabled. this is because when n is c hanged, the frequency of the low-freq uency base clock (ibase) will change proportionally until the digital loop filter has corrected the error. since the clock monitor uses ibase, it could erroneously detect an inactive clock. the clock monitor cannot be re-enabled until the internal clock is stable again (icgs is set). the following flow is an example of how to change the clock frequency: verify there is no clock monitor interrupt by reading the cmf bit. turn off the clock monitor. if desired, switch to the external clock (see 8.4.1 switching clock sources ). change the value of n. switch back to internal (see 8.4.1 switching clock sources ), if desired. turn on the clock monitor (see 8.4.2 enabling the clock monitor ), if desired. 8.4.6 nominal fr equency settling time because the clock period of the internal clock (iclk) is dependent on the digital loop filter outputs (ddiv and dstg) which cannot change instantaneously, iclk temporarily will operate at an incorrect clock period when any operating condition changes. this happens whenever the part is reset, the icg multiply factor (n) is changed, the icg trim factor (trim) is c hanged, or the internal clock is enabled after inactivity (stop mode or disabled operation). the time that the iclk takes to adjust to the correct period is known as the settling time. settling time depends primarily on how many correcti ons it takes to change the clock period and the period of each correction. since the corrections r equire four periods of the low-frequency base clock (4* ibase ), and since iclk is n (the icg multiply factor for the desired frequency) times faster than ibase, each correction takes 4*n* iclk . the period of iclk, however, will vary as the corrections occur. 8.4.6.1 settling to within 15 percent when the error is greater than 15 percent, the filter takes eight corrections to double or halve the clock period. due to how the dco increases or decreases the clock period, the total period of these eight corrections is approximately 11 times the period of the fastest correction. (if the corrections were perfectly linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly nonlinear.) therefore, the total time it takes to double or halve the clock period is 44*n* iclkfast .
usage notes mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 93 if the clock period needs more than doubled or halved, the same relationship applies, only for each time the clock period needs doubled, the total number of cycl es doubles. that is, when transitioning from fast to slow, going from the initial speed to half speed takes 44*n* iclkfast ; from half speed to quarter speed takes 88*n* iclkfast ; going from quarter speed to eighth speed takes 176*n* iclkfast ; and so on. this series can be expressed as (2 x ?1)*44*n* iclkfast , where x is the number of times the speed needs doubled or halved. since 2 x happens to be equal to iclkslow / iclkfast , the equation reduces to 44*n*( iclkslow ? iclkfast ). note that increasing speed takes much longer th an decreasing speed since n is higher. this can be expressed in terms of the initial clock period ( 1 ) minus the final clock period ( 2 ) as such: 8.4.6.2 settling to within 5 percent once the clock period is within 15 percent of the de sired clock period, the filter starts making smaller adjustments. when between 15 percent and 5 percent error, each correction will adjust the clock period between 1.61 percent and 2.94 percent. in this mode, a maximum of eight corrections will be required to get to less than 5 percent error. since the clock period is relatively close to desired, each correction takes approximately the same period of time, or 4* ibase . at this point, the internal clock stable bit (icgs) will be set and the clock frequency is usable, although the e rror will be as high as 5 percent. the total time to this point is: 8.4.6.3 total settling time once the clock period is within 5 percent of the desired clock period, the filter starts making minimum adjustments. in this mode, each correction will adjust the frequency between 0.202 percent and 0.368 percent. a maximum of 24 corrections will be required to get to the minimum error. each correction takes approximately the same period of time, or 4* ibase . added to the corrections for 15 percent to 5 percent, this makes 32 corrections (128* ibase ) to get from 15 percent to the minimum error. the total time to the minimum error is: the equations for 15 , 5 , and tot are dependent on the actual initial and final clock periods 1 and 2 , not the nominal. this means the variability in the ic lk frequency due to process, temperature, and voltage must be considered. additionally, other process factors and noise can affect the actual tolerances of the points at which the filter changes modes. this means a worst case adjustment of up to 35 percent (iclk clock period tolerance plus 10 percent) must be ad ded. this adjustment can be reduced with trimming. table 8-3 shows some typical values for settling time. table 8-3. typical settling time examples 1 2 n 15 5 tot 1/ (6.45 mhz) 1/ (25.8 mhz) 84 430 s 535 s 850 s 1/ (25.8 mhz) 1/ (6.45 mhz) 21 107 s 212 s 525 s 1/ (25.8 mhz) 1/ (307.2 khz) 1 141 s 246 s 560 s 1/ (307.2 khz) 1/ (25.8 mhz) 84 11.9 ms 12.0 ms 12.3 ms 15 abs 44n 1 2 ? () [] = 5 abs 44n 1 2 ? () [] 32 ibase + = tot abs 44n 1 2 ? () [] 128 ibase + =
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 94 freescale semiconductor 8.4.7 trimming fr equency on the inter nal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, will vary as much as 25 percent due to process, temperature, and voltage dependencies. these dependencies are in the voltage and current references, the offset of the comparators, and the internal capacitor. the method of changing the unadjusted operating point is by changing the size of the capacitor. this capacitor is designed with 639 equally sized units. of that number, 384 of these units are always connected. the remaining 255 units are put in by adjus ting the icg trim factor (trim). the default value for trim is $80, or 128 units, making the default c apacitor size 512. each unit added or removed will adjust the output frequency by about 0.195 percent of the unadjusted frequency (adding to trim will decrease frequency). theref ore, the frequency of ibase can be changed to 25 percent of its unadjusted value, which is enough to cancel th e process variability mentioned before. the best way to trim the internal clock is to use th e timer to measure the width of an input pulse on an input capture pin (this pulse must be supplied by the application and should be as long or wide as possible). considering the prescale value of the time r and the theoretical (zero error) frequency of the bus (307.2 khz *n/4), the error can be calculated. this e rror, expressed as a percentage, can be divided by 0.195 percent and the resultant factor added or subtracted from trim. this process should be repeated to eliminate any residual error. 8.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 8.5.1 wait mode the icg remains active in wait mode. if enabled, the icg interrupt to the cpu can bring the mcu out of wait mode. in some applications, low power-consumption is desir ed in wait mode and a high-frequency clock is not needed. in these applications, reduce power consumpti on by either selecting a low-frequency external clock and turn the internal clock generator off or redu ce the bus frequency by minimizing the icg multiplier factor (n) before executing the wait instruction. 8.5.2 stop mode the value of the oscillator enable in stop (oscen instop) bit in the config determines the behavior of the icg in stop mode. if osceninstop is low, t he icg is disabled in stop and, upon execution of the stop instruction, all icg activity will cease an d the output clocks (cgmxclk, cgmout, and tbmclk) will be held low. power consumption will be minimal. if osceninstop is high, the icg is enabled in stop and activity will continue. this is useful if the timebase module (tbm) is required to bring the mcu out of stop mode. icg interrupts will not bring the mcu out of stop mode in this case. during stop mode, if osceninstop is low, several fu nctions in the icg are affected. the stable bits (ecgs and icgs) are cleared, which will enable the external clock stabilization divider upon recovery. the clock monitor is disabled (cmon = 0) which will also clear the clock monitor interrupt enable (cmie) and clock monitor flag (cmf) bits. the cs, icgon , ecgon, n, trim, ddiv, and dstg bits are unaffected.
config options mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 95 8.6 config options four config options affect the functionality of the icg. these options are: 1. extclken, external clock enable 2. extxtalen, external crystal enable 3. extslow, slow external clock 4. osceninstop, oscillator enable in stop all config options will have a default setting. refer to chapter 5 configuration registers (config1 and config2) on how the config is used. 8.6.1 external cl ock enable (extclken) external clock enable (extclken), when set, enables the ecgon bit to be set. ecgon turns on the external clock input path through the ptc4/osc1 pin. when extclken is clear, ecgon cannot be set and ptc4/osc1 will always perform the ptc4 function. the default state for this option is clear. 8.6.2 external cryst al enable (extxtalen) external crystal enable (extxtalen), when set, will enable an amplifier to drive the ptc3/osc2 pin from the ptc4/osc1 pin. the amplifier will drive on ly if the external clock enable (extclken) bit and the ecgon bit are also set. if ext clken or ecgon are clear, ptc3/osc2 will perform the ptc3 function. when extxtalen is clear, ptc3/osc2 will always perform the ptc3 function. extxtalen, when set, also configures the clock monitor to expect an exte rnal clock source in the valid range of crystals (30 khz to 100 khz or 1 mhz to 8 mhz). when extxtalen is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 hz to 32 mhz). extxtalen, when set, also configures the external cl ock stabilization divider in the clock monitor for a 4096 cycle timeout to allow the pr oper stabilization time for a crystal. when extxtalen is clear, the stabilization divider is configured to 16 cycles sinc e an external clock source does not need a startup time. the default state for this option is clear. 8.6.3 slow external clock (extslow) slow external clock (extslow), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 khz?100 khz) if properly enabled with the external clock enable (extclken) and external crystal enable (extxtalen) bits. when clear, extslow enables high-frequency crystal operation (1 mhz to 8 mhz). extslow, when set, also configures the clock monitor to expect an external clock source that is slower than the low-frequency base clock (60 hz to 307.2 khz). when extslow is clear, the clock monitor will expect an external clock faster than the lo w-frequency base clock (307.2 khz to 32 mhz). the default state for this option is clear.
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 96 freescale semiconductor 8.6.4 oscillator enable in stop (osceninstop) oscillator enable in stop (oscenin stop), when set, will enable the icg to continue to generate clocks (either cgmxclk, cgmout, or tbmclk) in stop mo de. this function is used to keep the timebase running while the rest of the microcontroller stops . when osceninstop is clear, all clock generation will cease and cgmxclk, cgmout, and tbmclk will be forced low during stop mode. the default state for this option is clear. 8.7 input/output (i/o) registers the icg contains five regi sters. these registers are: 1. icg control register, icgcr 2. icg multiplier register, icgmr 3. icg trim register, icgtr 4. icg dco divider control register, icgdvr 5. icg dco stage control register, icgdsr several of the bits in these registers have interacti on where the state of one bit may force another bit to a particular state or prevent another bit from being set or cleared. a summary of this interaction is shown in table 8-4 . table 8-4. icg module register bit interaction summary condition register bit results for given condition cmie cmf cmon cs icgon icgs ecqon ecq n[ 6:0] trim[7:0] ddiv[3:0] dstq[7:0] reset 0 0 0 0 1 0 0 0 $15 $80 ? ? osceninstop = 0, stop = 1 00 0?? 0 ? 0? ? ? ? extclken = 0 0 0 0 0 1 ? 0 0 ? ? uw uw cmf = 1 ? (1) 1 ? 1 ? 1 ? uw uw uw uw cmon = 0 0 0 (0) ? ? ? ? ? ? ? ? ? cmon = 1 ? ? (1) ? 1 ? 1 ? uw uw uw uw cs = 0 ? ? ? (0) 1 ? ? ? ? ? uw uw cs = 1 ? ? ? (1) ? ? 1 ? ? ? ? ? icgon = 0 0 0 0 1 (0) 0 1 ? ? ? ? ? icgon = 1 ? ? ? ? (1) ? ? ? ? ? uw uw icgs = 0 us ? us uc ? (0) ? ? ? ? ? ? ecgon = 0 0 0 0 0 1 ? (0) 0 ? ? uw uw ecgs = 0 us ? us us ? ? ? (0) ? ? ? ? ioff = 1 ? 1* (1) 1 (1) 0 (1) ? uw uw uw uw eoff = 1 ? 1* (1) 0 (1) ? (1) 0 uw uw uw uw n = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? trim = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? ? register bit is unaffected by the given condition. 0, 1 register bit is forced clear or set (respectively) in the given condition. 0*, 1* register bit is temporarily forced clear or set (respectively) in the given condition. (0), (1) register bit must be clear or set (respectively) for the given condition to occur. us, uc, uw register bit cannot be set, cleared, or written (respectively) in the given condition.
input/output (i/o) registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 97 8.7.1 icg c ontrol register the icg control register (icgcr) contains the contro l and status bits for the internal clock generator, external clock generator, and clock monitor as well as the clock select and interrupt enable bits. cmie ? clock monitor interrupt enable bit this read/write bit enables clock monitor interrupts. an interrupt will occur when both cmie and cmf are set. cmie can be set when the cmon bit has been set for at least one cycle. cmie is forced clear when cmon is clear or during reset. 1 = clock monitor interrupts enabled 0 = clock monitor interrupts disabled cmf ? clock monitor interrupt flag this read-only bit is set when the clock monitor deter mines that either iclk or eclk becomes inactive and the cmon bit is set. this bit is cleared by first re ading the bit while it is set, followed by writing the bit low. this bit is forced clear when cmon is clear or during reset. 1 = either iclk or eclk has become inactive. 0 = iclk and eclk have not become inactive since th e last read of the icgcr, or the clock monitor is disabled. cmon ? clock monitor on bit this read/write bit enables the clock monitor. cm on can be set when both iclk and eclk have been on and stable for at least one bus cycle. (icgon, ecgon, icgs, and ecgs are all set.) cmon is forced set when cmf is set, to avoid inadvertent clea ring of cmf. cmon is forced clear when either icgon or ecgon is clear, during stop mode with osceninstop low, or during reset. 1 = clock monitor output enabled 0 = clock monitor output disabled cs ? clock select bit this read/write bit determines which clock will gener ate the oscillator output clock (cgmxclk). this bit can be set when ecgon and ecgs have been set for at least one bus cycle and can be cleared when icgon and icgs have been set for at least one bus cycle. this bit is forced set when the clock monitor determines the internal clock (iclk) is inacti ve or when icgon is clear. this bit is forced clear when the clock monitor determines t hat the external clock (eclk) is inactive, when ecgon is clear, or during reset. 1 = external clock (eclk) sources cgmxclk 0 = internal clock (iclk) sources cgmxclk address: $0036 bit 7654321bit 0 read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 (1) reset:00001000 1. see cmf bit description for method of clearing cmf bit. = unimplemented figure 8-11. icg control register (icgcr)
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 98 freescale semiconductor icgon ? internal clock generator on bit this read/write bit enables the internal clock generator. icgon can be cleared when the cs bit has been set and the cmon bit has been clear for at least one bus cycle. icgon is forced set when the cmon bit is set, the cs bit is clear, or during reset. 1 = internal clock generator enabled 0 = internal clock generator disabled icgs ? internal clock generator stable bit this read-only bit indicates when the internal clock generator has determined that the internal clock (iclk) is within about 5 percent of the desired valu e. this bit is forced clear when the clock monitor determines the iclk is inactive , when icgon is clear, when the icg multiplier register (icgmr) is written, when the icg trim register (icgtr) is written, during stop mode with osceninstop low, or during reset. 1 = internal clock is within 5 percent of the desired value. 0 = internal clock may not be within 5 percent of the desired value. ecgon ? external clock generator on bit this read/write bit enables the external clock generator. ecgon can be cleared when the cs and cmon bits have been clear for at least one bus cycl e. ecgon is forced set when the cmon bit or the cs bit is set. ecgon is forced clear during reset. 1 = external clock generator enabled 0 = external clock generator disabled ecgs ? external clock generator stable bit this read-only bit indicates when at least 4096 exter nal clock (eclk) cycles have elapsed since the external clock generator was enabled. this is not an assurance of the stability of eclk but is meant to provide a startup delay. this bit is forced clear when the clock monitor determ ines eclk is inactive, when ecgon is clear, during stop mode with osceninstop low, or during reset. 1 = 4096 eclk cycles have elapsed since ecgon was set. 0 = external clock is unstabl e, inactive, or disabled. 8.7.2 icg multiplier register n6:n0 ? icg multiplier factor bits these read/write bits change the multiplier used by the internal clock generator. the internal clock (iclk) will be: (307.2 khz 25 percent) * n a value of $00 in this register is interpreted the same as a value of $01. this register cannot be written when the cmon bit is set. reset sets this factor to $15 (decimal 21) for default frequency of 6.45 mhz 25 percent (1.613 mhz 25 percent bus). address: $0037 bit 7654321bit 0 read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 = unimplemented figure 8-12. icg multiplier register (icgmr)
input/output (i/o) registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 99 8.7.3 icg trim register trim7:trim0 ? icg trim factor bits these read/write bits change the size of the internal capacitor used by the internal clock generator. by testing the frequency of the internal clock and increm enting or decrementing this factor accordingly, the accuracy of the internal clock can be improved (see 20.9.1 trimmed internal clock generator characteristics ). incrementing this register by one decreases the frequency by 0.195 percent of the unadjusted value. decrementing this register by one increases the frequency by 0.195 percent. this register cannot be written when the cmon bit is se t. reset sets these bits to $80, centering the range of possible adjustment. 8.7.4 icg trim value this register provides non-volatile storage for an opti onal oscillator trim value, which can be transferred by the user software to the icg trim register (icgtr) when the device comes out of reset. (see 8.7.3 icg trim register .) 8.7.5 icg dco divider register ddiv3:ddiv0 ? icg dco divider control bits these bits indicate the number of divide-by-twos ( ddiv) that follow the digitally controlled oscillator. when icgon is set, ddiv is controlled by the digital loop filter. the range of valid values for ddiv is from $0 to $9. values of $a through $f are interpreted the same as $9. since the dco is active during reset, reset has no effect on dstg and the value may vary. address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 8-13. icg trim register (icgtr) address: $ff80 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 8-14. internal oscillator trim value (icgt) address: $0039 bit 7654321bit 0 read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000 uuuu = unimplemented u = unaffected figure 8-15. icg dco divider control register (icgdvr)
internal clock gene rator (icg) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 100 freescale semiconductor 8.7.6 icg dco stage register dstg7:dstg0 ? icg dco stage control bits these bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. the total number of stages is approximately equal to $1ff, so changing dstg from $00 to $ff will approximately double the period. incrementing ds tg will increase the period (decrease the frequency) by 0.202 percent to 0.368 percent (dec rementing has the opposite effect). dstg cannot be written when icgon is set to prevent inadvert ent frequency shifting. when icgon is set, dstg is controlled by the digital loop filter. since the dco is active during reset, reset has no effect on dstg and the value may vary. address: $003a bit 7654321bit 0 read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr reset: unaffected by reset r= reserved figure 8-16. icg dco stage control register (icgdsr)
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 101 chapter 9 external interrupt (irq) 9.1 introduction this section describes the non-maskable external interrupt (irq ) input. 9.2 features features include: dedicated external interrupt pin (irq ) hysteresis buffer programmable edge-only or edge- and level-interrupt sensitivity automatic interrupt acknowledge 9.3 functional description a logic 0 applied to the external interrupt pin can latch a central processor unit (cpu) interrupt request. figure 9-1 shows the structure of the irq module. figure 9-1. irq block diagram ack imask dq ck clr irq high interrupt to mode select logic irq latch request irq v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus
external interrupt (irq) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 102 freescale semiconductor interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of these actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a 1 to the ack bit clears the irq latch. reset ? a reset automatically clears both interrupt latches. the external interrupt pin is fa lling-edge triggered and is software- configurable to be both falling-edge and low-level triggered. the mode bit in the iscr co ntrols the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of these occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the iscr masks all exter nal interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the co rresponding imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including exte rnal interrupt requests. see figure 9-2 . 9.4 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with mode set, both of these actions must occur to clear the irq latch: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latc h. writing to the ack bit can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge on irq that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu load s the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, the irq latch remains set. the vector fetch or software clear and the return of the irq pin to logic 1 can occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low.
irq pin mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 103 figure 9-2. irq interrupt flowchart if the mode bit is clear, the irq pin is falling-edge sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. from reset i bit set? fetch next yes no interrupt? instruction swi instruction? rti instruction? no stack cpu registers no set i bit load pc with interrupt vector no yes unstack cpu registers execute instruction yes yes
external interrupt (irq) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 104 freescale semiconductor 9.5 irq module duri ng break interrupts the system integration module (sim) controls whether the irq interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latches during the break state. to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 9.6 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has these functions: shows the state of the irq interrupt flag clears the irq interrupt latch masks irq interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001d bit 7654321bit 0 read:0000irqf0 imask mode write:rrrrrack reset:00000000 r= reserved figure 9-3. irq status and control register (iscr)
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 105 chapter 10 keyboard interrupt (kbd) module 10.1 introduction the keyboard interrupt (kbd) module provides five independently maskable external interrupt pins. 10.2 features kbd features include: five keyboard interrupt pins (pta4/kbd4 ?pta0/kbd0 ) with internal pullups, with separate keyboard interrupt enable bits and one keyboard interrupt mask hysteresis buffers programmable edge only or edge and level interrupt sensitivity automatic interrupt acknowledge exit from low-power modes 10.3 functional description writing to the kbie4?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port as a keyboard interrupt pin. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyb oard pins goes low after all were high. the modek bit in the keyboard status and control register cont rols the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge and low level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control re gister (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe4 and $ffe5. return of all enabled keyboard interrupt pins to logic 1. as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
keyboard interrupt (kbd) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 106 freescale semiconductor figure 10-1. block diagram highlighting keyboard block and pins single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 107 figure 10-2. keyboard module block diagram the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. kb0ie kb4ie . . . keyboard interrupt dq ck clr v dd modek imaskk keyboard interrupt ff request vector fetch decoder ackk internal bus reset to pullup kbd4 kbd0 to pullup keyf enable enable synchronizer
keyboard interrupt (kbd) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 108 freescale semiconductor 10.4 keyboard initialization when a keyboard interrupt pin is enabled, it takes time fo r the internal pullup to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bi t in the keyboard status and control register 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddra bits in data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 10.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 10.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 10.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 10.6 keyboard module during break interrupts the bcfe bit in the break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear the keyf bit during a brea k interrupt, write a 1 to the bcfe bit. if keyf is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the keyf bit during the break state, write a 0 to the bcfe bit. with bcfe at 0, writing to the keyboard acknowledge bit (ackk) in the keyboard stat us and control register during the break state has no effect. see 10.7.1 keyboard status and control register .
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 109 10.7 i/o registers these registers control and monitor operation of the keyboard module: keyboard status and control register, kbscr keyboard interrupt enable register, kbier 10.7.1 keyboard stat us and control register the keyboard status and control register: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 10-3. keyboard status and control register (kbscr)
keyboard interrupt (kbd) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 110 freescale semiconductor 10.7.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin. kbie4?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbdx pin enabled as keyboard interrupt pin 0 = kbdx pin not enabled as keyboard interrupt pin address: $001b bit 7654321bit 0 read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 10-4. keyboard interrupt enable register (kbier)
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 111 chapter 11 low-voltage inhibit (lvi) module 11.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 11.2 features features include: programmable lvi reset programmable power consumption 3 v or 5 v selectable trip point 11.3 functional description figure 11-1 shows the structure of the lvi module. the lvi is enabled out of reset. the following bits, located in the configuration regist er, can alter the default conditions. setting the lvi power disable bit, lvipwrd, disables the lvi. setting the lvi reset disable bit, lvirstd, pr events the lvi module from generating a reset. setting the lvi enable in stop mode bit, lvistop, enables the lvi to continue monitoring the voltage level on v dd , while in stop mode. figure 11-1. lvi module block diagram low v dd lvirstd v dd > lvi tripr = 0 v dd < lvi tripf = 1 lviout detector v dd lvi reset from config-1 from config-1 lvipwrd lvi5or3 from config-1 lvistop from config-1 stop instruction
low-voltage inhibit (lvi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 112 freescale semiconductor once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr . v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset (see 11.3.2 forced reset operation ). the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. 11.3.1 polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bit. in the configuration regist er, the lvipwrd bit must be at 0 to enable the lvi module, and the lvirstd bit must be at 1 to disable lvi resets. 11.3.2 forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the lvi tripf level. in the configuration register, the lvipwrd and lvirstd bits must be at 0 to enabl e the lvi module and to enable lvi resets. 11.3.3 false reset protection false reset protection is provided by the hyst eresis in the lvi trip circuit (refer to table 11-1 ). please refer to 20.5 dc electrical characteristics for hysteresis value (vhys) and rising and falling lvi trip values. 11.3.4 lvi status register the lvi status register flags v dd voltages below the lvi tripf level . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the lvi tripf voltage. (see table 11-1 .) reset clears the lviout bit. address: $fe0c bit 7654321bit 0 read:lviout0000000 write: reset:00000000 = unimplemented figure 11-2. lvi status register (lvisr) table 11-1. lviout bit indication v dd lviout at level: v dd > lvi tripr 0 v dd < lv i tripf 1 lv i tripf < v dd < lv i tripr previous value
lvi interrupts mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 113 11.4 lvi interrupts the lvi module does not generate interrupt requests. 11.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 11.5.1 wait mode with the lvipwrd bit in the configuration register programmed to 0, the lvi module is active after a wait instruction. with the lvirstd bit in the confi guration register programmed to 0, the lvi module can generate a reset and bring the mcu out of wait mode. 11.5.2 stop mode with the lvistop bit in the configuration register programmed to a 1, and the lvipwrd bit programmed to a 0, the lvi module will be active after a stop instruction. with the lvipwrd bit in the configuration regist er programmed to 1, and the lvistop bit programmed to a 0, the lvi module will be inactive after a stop instruction.
low-voltage inhibit (lvi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 114 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 115 chapter 12 input/output (i/o) ports (ports) 12.1 introduction twenty-four bidirectional input/output (i/o) pins form five parallel ports. all i/o pins are programmable as inputs or outputs. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 12.2 port a port a is a 7-bit general-purpose bidirectional i/o port that shares pin functions with the serial peripheral interface (spi) and keyboard (kbd) modules. 12.2.1 port a data register the port a data register contains a data latch for each of the seven port a pins. pta[6:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. 12.2.2 data dir ection register a data direction register a determines whether each port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the correspondi ng port a pin; a 0 disables the output buffer. address: $0000 bit 7654321bit 0 read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: ss spsck kbd4 kbd3 kbd2 kbd1 kbd0 = unimplemented figure 12-1. port a data register (pta)
input/output (i/o) ports (ports) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 116 freescale semiconductor ddra[6:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[6:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 12-3 shows the port a i/o logic. figure 12-3. port a i/o circuit when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-1 summarizes the operation of the port a pins. address: $0004 bit 7654321bit 0 read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 = unimplemented figure 12-2. data direction register a (ddra) table 12-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x input, hi-z ddra[6:0] pin pta[6:0] (1) 1 x output ddra[6:0] pta[6:0] pta[6:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
port b mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 117 12.3 port b port b is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter (adc) and some pin functions with timb. port b is designed so that the adc function will take priority over the timer functionality on ptb6 and ptb7. if the adc is selected for a conversion on a previously enabled timer pin, the port pin will be connected to the adc and disconnected from the timer. if both the timer input capture and adc functions are being used on the same port pin, it is recommended that the timer channel be diabled before the pin is enabled as an adc input to avoid glitches. if both the timer output compare (or pwm) and adc functions are being used on the same port pin, it is recommended that the timer channel be disabled before the pin is enabled as an adc input. 12.3.1 port b data register the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. ad[7:0] ? adc channels ptb7?ptb0 are eight adc channels. the adc channel select bits, ch[4:0], determine whether the ptb7?ptb0 pins are adc channels or general-purpos e i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be a 0 if the data direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch (see chapter 3 analog-to-digital converter (adc) module ). ddrb does not affect the data direction of port b pins that are being used by the adc. however, the ddrb bits always determine whether reading port b returns to the states of the latches or 0. tbch[1:0] ? timer channel i/o bits the ptb7/tbch1?ptb6/tbch0 pins are the timb input capture/output compare pins. the edge/level select bits, elsxb?elsxa, determine whether the ptb7/tbch1?ptb6/tbch0 pins are timer channel i/o pins or general-purpose i/o pins. see 18.8.1 timb status and control register . note data direction register b (ddrb) does not affect the data direction of port b pins that are being used by the timb. however, the ddrb bits always determine whether reading port b returns the states of the latches or the states of the pins. see table 12-2 . address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 alternative function: tbch1 tbch0 figure 12-4. port b data register (ptb)
input/output (i/o) ports (ports) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 118 freescale semiconductor 12.3.2 data dir ection register b data direction register b determines whether each port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the correspondi ng port b pin; a 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 12-6 shows the port b i/o logic. figure 12-6. port b i/o circuit when ddrbx is a 1, reading address $0001 reads the ptbx data latch. when ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-5. data direction register b (ddrb) table 12-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x input, hi-z ddrb[7:0] pin ptb[7:0] (1) 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
port c mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 119 12.4 port c port c is an 5-bit general-purpose bidirectional i/o por t that shares pin functions with the internal clock generator (icg) and serial peripheral interface (spi) modules. 12.4.1 port c data register the port c data register contains a data latch for each of the five port c pins. ptc[4:0] ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. mclk ? t12 system clock bit the system clock is driven out of ptc2 when enabled by mclken bit in ptcddr7. 12.4.2 data dir ection register c data direction register c determines whether each port c pin is an input or an output. writing a 1 to a ddrc bit enables the output buffer for the correspondi ng port c pin; a 0 disables the output buffer. mclken ? mclk enable bit this read/write bit enables mclk to be an output signal on ptc2. if mclk is enabled, ptc2 is under the control of mclken. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled address: $0002 bit 7654321bit 0 read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: osc1 osc2 mclk mosi miso = unimplemented figure 12-7. port c data register (ptc) address: $0006 bit 7654321bit 0 read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 12-8. data direction register c (ddrc)
input/output (i/o) ports (ports) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 120 freescale semiconductor ddrc[4:0] ? data direction register c bits these read/write bits control port c data directi on. reset clears ddrc[4:0] and mclken, configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. figure 12-9 shows the port c i/o logic. figure 12-9. port c i/o circuit when bit ddrcx is a 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port c pins. 12.5 port d port d is a 2-bit special function port that shares its pins with the timer interface module (tima). 12.5.1 port d data register the port d data register contains a data latch for each of the two port d pins. table 12-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 2 input, hi-z ddrc[7] pin ptc2 1 2 output ddrc[7] 0 ? 0 x input, hi-z ddrc[4:0] pin ptc[4:0] (1) 1 x output ddrc[4:0] ptc[4:0] ptc[4:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus
port d mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 121 ptd[1:0] ? port d data bits ptd[1:0] are read/write, software programmable bits . data direction of each port d pin is under the control of the corresponding bit in data direction register d. tach[1:0] ? timer channel i/o bits the ptd1/tach1?ptd0/tach0 pins are the tima input capture/output compare pins. the edge/level select bits, elsxb?elsxa, determine whether the ptd1/tach1?ptd0/tach0 pins are timer channel i/o pins or general-purpose i/o pins. see 17.8.1 tima status and control register . note data direction register d (ddrd) does not affect the data direction of port d pins that are being used by the tima. however, the ddrd bits always determine whether reading port d returns the states of the latches or the states of the pins. see table 12-4 . 12.5.2 data dir ection register d data direction register d determines whether each port d pin is an input or an output. writing a 1 to a ddrd bit enables the output buffer for the correspondi ng port d pin; a 0 disables the output buffer. ddrd[1:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[1:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. address: $0003 bit 7654321bit 0 read:000000 ptd1 ptd0 write: reset: unaffected by reset alternative function: tach1 tach0 = unimplemented figure 12-10. port d data register (ptd) address: $0007 bit 7654321bit 0 read:000000 ddrd1 ddrd0 write: reset:00000000 = unimplemented figure 12-11. data direction register d (ddrd)
input/output (i/o) ports (ports) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 122 freescale semiconductor figure 12-12 shows the port d i/o logic. figure 12-12. port d i/o circuit when bit ddrdx is a 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port d pins. 12.6 port e port e is a 2-bit special function port that shares its pins with the enhanc ed serial communications interface module (esci). 12.6.1 port e data register the port e data register contains a data latch for each of the port e pins. table 12-4. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x input, hi-z ddrd[1:0] pin ptd[1:0] (1) 1 x output ddrd[1:0] ptd[1:0] ptd[1:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. address: $0008 bit 7654321bit 0 read:000000 pte1 pte0 write: reset: unaffected by reset alternative function: rxd txd = unimplemented figure 12-13. port e data register (pte) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus
port e mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 123 pte[1:0] ? port e data bits these read/write bits are software programmable. data direction of each port e pin is under the control of the corresponding bit in data direction regi ster e. reset has no effect on pte[1:0]. rxd ? sci receive data input bit the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see 13.8.1 esci control register 1 . txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. see 13.8.1 esci control register 1 . note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the esci. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 12-5 . 12.6.2 data dir ection register e data direction register e determines whether each port e pin is an input or an output. writing a 1 to a ddre bit enables the output buffer for the correspondi ng port e pin; a 0 disables the output buffer. ddre[1:0] ? data direction register e bits these read/write bits contro l port e data direction. reset clears ddre[1:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction regist er e bits from 0 to 1. address: $000a bit 7654321bit 0 read:000000 ddre1 ddre0 write: reset:00000000 = unimplemented figure 12-14. data direction register e (ddre)
input/output (i/o) ports (ports) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 124 freescale semiconductor figure 12-15 shows the port e i/o logic. figure 12-15. port e i/o circuit when bit ddrex is a 1, reading address $0008 reads the ptex data latch. when bit ddrex is a 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-5 summarizes the operation of the port e pins. table 12-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x input, hi-z ddre[1:0] pin pte[1:0] (1) 1 x output ddre[1:0] pte[1:0] pte[1:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddre ($000a) write ddre ($000a) reset write pte ($0008) read pte($0008) ptex ddrex ptex internal data bus
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 125 chapter 13 enhanced serial communications interface (esci) module 13.1 introduction the enhanced serial communications interface (esc i) module allows asynchronous communications with peripheral devices and other microcontroller units (mcu). 13.2 features features include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter centra l processor unit (cpu) interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection 13.3 pin name conventions the generic names of the esci input/output (i/o) pins are: rxd (receive data) txd (transmit data)
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 126 freescale semiconductor figure 13-1. block diagram highlighting esci block and pins esci i/o lines are implemented by s haring parallel i/o port pins. the full name of an esci input or output reflects the name of the shared port pin. table 13-1 shows the full names and the generic names of the esci i/o pins. the generic pin names appear in the text of this section. table 13-1. pin name conventions generic pin names rxd txd full pin names pte1/rxd pte0/txd single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 127 13.4 functional description figure 13-2 shows the structure of the esci module. t he esci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote dev ices, including other mcus. the transmitter and receiver of the esci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the esci, writes the data to be transmitted, and processes received data. the baud rate clock source for the esci can be selected via the configuration bit, escibdsrc, of the config2 register ($001e). figure 13-2. esci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf esci data receive shift register esci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator bus clock rxd txd enhanced pre- arbiter- sci_txd rxd linr scaler cgmxclk escibdsrc from config2 sl sl=1 -> sci_clk = busclk sl=0 -> sci_clk = cgmxclk (4x busclk) sci_clk bus_clk aclk bit in sciactl sl
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 128 freescale semiconductor 13.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 13-3 . figure 13-3. sci data formats 13.4.2 transmitter figure 13-4 shows the structure of the sci transmitter. the baud rate clock source for the esci can be selected via the configuration bit, escibdsrc. figure 13-4. esci transmitter bit 5 bit 0 bit 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit next start bit next start bit stop bit stop bit 8-bit data format (bit m in scc1 clear) 9-bit data format (bit m in scc1 set) start bit start bit pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc bus clock parity generation msb esci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register tc sctie tcie scte transmitter cpu inter rupt request m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sci_txd pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 lint
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 129 13.4.2.1 character length the transmitter can accommodate either 8-bit or 9- bit data. the state of the m bit in esci control register 1 (scc1) determines character length. when tr ansmitting 9-bit data, bit t8 in esci control register 3 (scc3) is the ninth bit (bit 8). 13.4.2.2 character transmission during an esci transmission, the transmit shift regist er shifts a character out to the txd pin. the esci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an esci transmission: 1. enable the esci by writing a 1 to the enable esci bit (ensci) in esci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the trans mitter enable bit (te) in esci control register 2 (scc2). 3. clear the esci transmitter empty bit (scte) by first reading esci status register 1 (scs1) and then writing to the scdr. for 9-bit data, also write the t8 bit in scc3. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of 1s. after the preamble shifts out, cont rol logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into the least significant bit (lsb) position of the transmit shift register. a 1 stop bit goes into the most significant bit (msb) position. the esci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the esci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in esci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 13.4.2.3 break characters writing a 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. for txinv = 0 (output not inverted), a transmitted break character contains all 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1 and the linr bits in scbr. as long as sbk is at 1, transmitter logic conti nuously loads break charac ters into the transmit shift register. after software clears the sbk bit, the shift register finis hes transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. when linr is cleared in scbr, the esci recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be, resulting in a total of 10 or 11 consecutive 0 data bits. when linr is set in scbr, the esci recognizes a break character when a start bit is followed by 9 or 10 consecutive 0 data bits and a 0 where the st op bit should be, resulting in a total of 11 or 12 consecutive 0 data bits.
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 130 freescale semiconductor receiving a break character has these effects on esci registers: sets the framing error bit (fe) in scs1 sets the esci receiver full bit (scrf) in scs1 clears the esci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 13.4.2.4 idle characters for txinv = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. idle character length depends on the m bi t in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when a break sequence is followed immedi ately by an idle character, this sci design exhibits a condition in wh ich the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or ni ne data bits (as defined by the m bit in scc1) of 0 and one half data bit length of 0 in the stop bit position followed immediately by the idle character. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes da ta previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. 13.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in esci control regi ster 1 (scc1) reverses the polarity of transmitted data. all transmitted values including idle, break, start, and stop bits, are inverted when txinv is at 1. see 13.8.1 esci control register 1 . 13.4.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the esci transmitter: esci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the esci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests.
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 131 13.4.3 receiver figure 13-5 shows the structure of the esci receiver. figure 13-5. esci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu cpu interrupt esci data register r8 scrie ilie rwu scrf idle internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 rxd bus clock pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 linr request interrupt request orie neie feie peie or nf fe pe
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 132 freescale semiconductor 13.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit dat a. the state of the m bit in esci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in esci control register 3 (scc3) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 13.4.3.2 character reception during an esci reception, the receive shift register sh ifts characters in from the rxd pin. the esci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the esci receiver full bit, scrf, in esci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the esci rece ive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 13.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 13-6 ): after every start bit after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16. figure 13-6. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 133 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 13-2 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-3 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-4 summarizes the results of the stop bit samples. table 13-2. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 13-3. data bit recovery rt8, rt9, and rt10 samples d ata bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 13-4. stop bit recovery rt8, rt9, and rt10 samples f raming error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 134 freescale semiconductor 13.4.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at t he same time that the scrf bit is set. 13.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 13-7 shows how much a slow received characte r can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 13-7. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 13-7 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is: for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 13-7 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycl es = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% =
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 135 fast data tolerance figure 13-8 shows how much a fast received characte r can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 13-8. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 13-8 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 13-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 13.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: 1. address mark ? an address mark is a 1 in th e msb position of a received character. when the wake bit is set, an address mark wakes the receiv er from the standby st ate by clearing the rwu bit. the address mark also sets the esci receiver full bit, scrf. software can then compare the character containing the address mark to the user -defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. 2. idle input line condition ? when the wake bit is cl ear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90%. = 170 176 ? 170 ------------------------- - 100 3.53%. =
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 136 freescale semiconductor does not set the receiver idle bit, idle, or the esci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle will cause the receiver to wake up. 13.4.3.7 receiver interrupts these sources can generate cpu interrupt requests from the esci receiver: esci receiver full (scrf) ? the scrf bit in sc s1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the esci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 13.4.3.8 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate esci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when t he esci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate esci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate esci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the esci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate esci error cpu interrupt requests. 13.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 13.5.1 wait mode the esci module remains active in wait mode. any enabled cpu interrupt request from the esci module can bring the mcu out of wait mode. if esci module functions are not required during wait mode, reduce power consum ption by disabling the module before executing the wait instruction. 13.5.2 stop mode the esci module is inactive in stop mode. the stop instruction does not affect esci register states. esci module operation resumes after the mcu exits stop mode.
esci during break mo dule interrupts mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 137 because the internal clock is i nactive during stop mode, entering stop mode during an esci transmission or reception results in invalid data. 13.6 esci during br eak module interrupts the bcfe bit in the break flag control register (sbfcr) enables software to clear status bits during the break state. see 19.2 break module (brk) . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 13.7 i/o signals port e shares two of its pins with th e esci module. the two esci i/o pins are: pte0/txd ? transmit data pte1/rxd ? receive data 13.7.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from the esci transmitter. the esci shares the pte0/txd pin with port e. when the esci is enabled, the pte0/txd pin is an output regardless of the state of the ddre0 bit in data direction register e (ddre). 13.7.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the es ci receiver. the esci shares the pte1/rxd pin with port e. when the esci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). 13.8 i/o registers these i/o registers control and monitor esci operation: esci control register 1, scc1 esci control register 2, scc2 esci control register 3, scc3 esci status register 1, scs1 esci status register 2, scs2 esci data register, scdr esci baud rate register, scbr esci prescaler register, scpsc esci arbiter control register, sciactl esci arbiter data register, sciadat
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 138 freescale semiconductor 13.8.1 esci control register 1 esci control register 1 (scc1): enables loop mode operation enables the esci controls output polarity controls character length controls esci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the esci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable esci bit this read/write bit enables the esci and the esci baud rate generator. clearing ensci sets the scte and tc bits in esci status register 1 and disabl es transmitter interrupts. reset clears the ensci bit. 1 = esci enabled 0 = esci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit invert s all transmitted values including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether esci characters are eight or nine bits long (see table 13-5 ).the ninth bit can serve as a receiver wakeup signal or as a parity bit. reset clears the m bit. 1 = 9-bit esci characters 0 = 8-bit esci characters address: $0010 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 13-9. esci control register 1 (scc1)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 139 wake ? wakeup condition bit this read/write bit determines which condition wakes up the esci: a 1 (address mark) in the msb position of a received c haracter or an idle condition on t he rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the esci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the esci parity function (see table 13-5 ). when enabled, the parity function inserts a parity bit in the msb position (see table 13-3 ). reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the esc i generates and checks for odd parity or even parity (see table 13-5 ). reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. table 13-5. character format selection control bits character format m pen:pty start bits data bits pa rity stop bits character length 0 0 x 1 8 none 1 10 bits 1 0 x 1 9 none 1 11 bits 0 1 0 1 7 even 1 10 bits 0 1 1 1 7 odd 1 10 bits 1 1 0 1 8 even 1 11 bits 1 1 1 1 8 odd 1 11 bits
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 140 freescale semiconductor 13.8.2 esci control register 2 esci control register 2 (scc2): enables these cpu interrupt requests: ? scte bit to generate transmitter cpu interrupt requests ? tc bit to generate transmitter cpu interrupt requests ? scrf bit to generate receiver cpu interrupt requests ? idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables esci wakeup transmits esci break characters sctie ? esci transmit interrupt enable bit this read/write bit enables the scte bit to generat e esci transmitter cpu interrupt requests. setting the sctie bit in scc2 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate esci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? esci receive interrupt enable bit this read/write bit enables the scrf bit to generate esci receiver cpu interrupt requests. setting the scrie bit in scc2 enables the scrf bit to generate cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate esci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0011 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 13-10. esci control register 2 (scc2)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 141 te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 consecutive 1s from the transmit shift register to the txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (1). clearing and then setting te during a transmission queues an id le character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recogni tion of a valid start bit. if sbk remains set, the transmitter continuously transmits break c haracters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins caus es the esci to send a break character instead of a preamble.
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 142 freescale semiconductor 13.8.3 esci control register 3 esci control register 3 (scc3): stores the ninth esci data bit received and the ninth esci data bit to be transmitted. enables these interrupts: ? receiver overrun ? noise error ? framing error ? parity error r8 ? received bit 8 when the esci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the esci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the esci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. reset clears the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the receiver overrun bit, or. reset clears orie. 1 = esci error cpu interrupt requests from or bit enabled 0 = esci error cpu interrupt requests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = esci error cpu interrupt requests from ne bit enabled 0 = esci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = esci error cpu interrupt requests from fe bit enabled 0 = esci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = esci error cpu interrupt requests from pe bit enabled 0 = esci error cpu interrupt requests from pe bit disabled address: $0012 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:u0000000 = unimplemented r = reserved u = unaffected figure 13-11. esci control register 3 (scc3)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 143 13.8.4 esci status register 1 esci status register 1 (scs1) contai ns flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? esci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an esci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an esci transmitter cpu interrupt re quest. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an esci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble , or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of lat ency between queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? esci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the esci data register. scrf can generate an esci receiver cpu interrupt request. when the scrie bit in scc2 is set the scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an esci receiver cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must address: $0013 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 13-12. esci status register 1 (scs1)
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 144 freescale semiconductor receive a valid character that sets the scrf bit befo re an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character mu st again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an esci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 13-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. figure 13-13. flag clearing sequence in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 145 nf ? receiver noise flag bit this clearable, read-only bit is set when the esc i detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is al so set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an esci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the esci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected 13.8.5 esci status register 2 esci status register 2 (scs2) contai ns flags to signal these conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the esci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become se t again only after 1s agai n appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the esci module or entering stop mode can show whethe r a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0014 bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 13-14. esci status register 2 (scs2)
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 146 freescale semiconductor 13.8.6 esci data register the esci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the esci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $0015 accesses the read-only rece ived data bits, r7:r0. writing to address $0015 writes the data to be transmitted, t7:t0. re set has no effect on the esci data register. note do not use read-modify-write instructions on the esci data register. 13.8.7 esci baud rate register the esci baud rate register (scbr) together with the esci prescaler register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate. one in the esci baud rate register and one in the esci prescaler register. linr ? lin receiver bit this read/write bit selects the enhanced esci features for slave nodes in the local interconnect network (lin) protocol as shown in table 13-6 . reset clears linr. in lin (version 1.2) systems, the master node transmits a break charac ter which will appear as 11.05?14.95 dominant bits to the slave node. a dat a character of 0x00 sent from the master might appear as 7.65?10.35 dominant bit times. this is due to the oscillator tolerance requirement that the address: $0015 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 13-15. esci data register (scdr) address: $0016 bit 7654321bit 0 read: r linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 r = reserved figure 13-16. esci baud rate register (scbr) table 13-6. esci lin control bits linr m functionality 0 x normal esci functionality 1 0 13-bit break detect enabled for lin receiver 1 1 14-bit break detect enabled for lin receiver
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 147 slave node must be within 15% of the master node's oscillator. since a slave node cannot know if it is running faster or slower than the master node (pri or to synchronization), the linr bit allows the slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. the break symbol length must be verified in software in any case, but the linr bit serves as a filter, preventing false detections of break characte rs that are really 0x00 data characters. scp1 and scp0 ? esci baud rate register prescaler bits these read/write bits select the baud rate register prescaler divisor as shown in table 13-7 . reset clears scp1 and scp0. scr2?scr0 ? esci baud rate select bits these read/write bits select the esci baud rate divisor as shown in table 13-8 . reset clears scr2?scr0. esci prescaler register the esci prescaler register (scpsc) together with the esci baud rate register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate. one in the esci baud rate register and one in the esci prescaler register. table 13-7. esci baud rate prescaling scp[1:0] baud rate register prescaler divisor (bpd) 00 1 01 3 10 4 11 13 table 13-8. esci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 address: $0017 bit 7654321bit 0 read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 figure 13-17. esci prescaler register (scpsc)
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 148 freescale semiconductor pds2?pds0 ? prescaler divisor select bits these read/write bits select the prescaler divisor as shown in table 13-9 . reset clears pds2?pds0. note the setting of ?000? will bypass not only this prescaler but also the prescaler divisor fine adjust (pdfa). it is not recommended to bypass the prescaler while ensci is set, because the switching is not glitch free. pssb4?pssb0 ? clock insertion select bits these read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average prescaler frequency as shown in table 13-10 . reset clears pssb4?pssb0. use the following formula to calculate the esci baud rate: where: frequency of the sci clock source = f bus or cgmxclk (selected by escibdsrc in the config2 register) bpd = baud rate register prescaler divisor bd = baud rate divisor pd = prescaler divisor pdfa = prescaler divisor fine adjust table 13-11 shows the esci baud rates that can be generated with a 4.9152-mhz clock frequency. table 13-9. esci prescaler division ratio pds[2:1:0] prescaler divisor (pd) 0 0 0 bypass this prescaler 001 2 010 3 011 4 100 5 101 6 110 7 111 8 frequency of the sci clock source 64 x bpd x bd x (pd + pdfa) baud rate =
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 149 table 13-10. esci prescaler divisor fine adjust pssb[4:3:2:1:0] prescaler divisor fine adjust (pdfa) 00000 0/32 = 0 0 0 0 0 1 1/32 = 0.03125 0 0 0 1 0 2/32 = 0.0625 0 0 0 1 1 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 0 0 1 0 1 5/32 = 0.15625 0 0 1 1 0 6/32 = 0.1875 0 0 1 1 1 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 0 1 0 0 1 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.375 0 1 1 0 1 13/32 = 0.40625 0 1 1 1 0 14/32 = 0.4375 0 1 1 1 1 15/32 = 0.46875 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.875 1 1 1 0 1 29/32 = 0.90625 1 1 1 1 0 30/32 = 0.9375 1 1 1 1 1 31/32 = 0.96875
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 150 freescale semiconductor table 13-11. esci baud rate selection examples pds[2:1:0] pssb[4:3:2:1:0] scp[1:0] prescaler divisor (bpd) scr[2:1:0] baud rate divisor (bd) baud rate (esci clock = 4.9152 mhz) 0 0 0 x x x x x 0 0 1 0 0 0 1 76,800 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 111 00001 00 1 000 1 9562.65 111 00010 00 1 000 1 9525.58 111 11111 00 1 000 1 8563.07 0 0 0 x x x x x 0 0 1 0 0 1 2 38,400 0 0 0 x x x x x 0 0 1 0 1 0 4 19,200 0 0 0 x x x x x 0 0 1 0 1 1 8 9600 0 0 0 x x x x x 0 0 1 1 0 0 16 4800 0 0 0 x x x x x 0 0 1 1 0 1 32 2400 0 0 0 x x x x x 0 0 1 1 1 0 64 1200 000 xxxxx 00 1 111 128 600 0 0 0 x x x x x 0 1 3 0 0 0 1 25,600 0 0 0 x x x x x 0 1 3 0 0 1 2 12,800 0 0 0 x x x x x 0 1 3 0 1 0 4 6400 0 0 0 x x x x x 0 1 3 0 1 1 8 3200 0 0 0 x x x x x 0 1 3 1 0 0 16 1600 0 0 0 x x x x x 0 1 3 1 0 1 32 800 0 0 0 x x x x x 0 1 3 1 1 0 64 400 000 xxxxx 01 3 111 128 200 0 0 0 x x x x x 1 0 4 0 0 0 1 19,200 0 0 0 x x x x x 1 0 4 0 0 1 2 9600 0 0 0 x x x x x 1 0 4 0 1 0 4 4800 0 0 0 x x x x x 1 0 4 0 1 1 8 2400 0 0 0 x x x x x 1 0 4 1 0 0 16 1200 0 0 0 x x x x x 1 0 4 1 0 1 32 600 0 0 0 x x x x x 1 0 4 1 1 0 64 300 000 xxxxx 10 4 111 128 150 0 0 0 x x x x x 1 1 13 0 0 0 1 5908 0 0 0 x x x x x 1 1 13 0 0 1 2 2954 0 0 0 x x x x x 1 1 13 0 1 0 4 1477 0 0 0 x x x x x 1 1 13 0 1 1 8 739 0 0 0 x x x x x 1 1 13 1 0 0 16 369 0 0 0 x x x x x 1 1 13 1 0 1 32 185 000 xxxxx 11 13 110 64 92 0 0 0 x x x x x 1 1 13 1 1 1 128 46
esci arbiter mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 151 13.9 esci arbiter the esci module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time det ection. the arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. the cpu can control operation mode via the esci arbiter control register (sciactl). 13.9.1 esci arbite r control register am1 and am0 ? arbiter mode select bits as shown in table 13-12 , these read/write bits select the mode of the arbiter module. reset clears am1 and am0. alost ? arbitration lost flag this read-only bit indicates loss of arbitration. clear alost by writing a 0 to am1. reset clears alost. aclk ? arbiter counter clock select bit this read/write bit selects the arbiter counter clock source. reset clears aclk. 1 = arbiter counter is clocked with one quarte r of the esci input clock generated by the esci prescaler. 0 = arbiter counter is clocked wi th the bus clock divided by four note for aclk=1, the arbiter input clock is driven from the esci prescaler. the prescaler can be clocked by either the bus clock or cgmxclk depending on the state of the escibdsrc bit in config2. afin? arbiter bit time measurement finish flag this read-only bit indicates bit ti me measurement has finished. clea r afin by writing any value to sciactl. reset clears afin. 1 = bit time measurement has finished 0 = bit time measurement not yet finished address: $0018 bit 7654321bit 0 read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 = unimplemented figure 13-18. esci arbiter control register (sciactl) table 13-12. esci arbiter selectable modes am[1:0] esci arbiter mode 0 0 idle / counter reset 0 1 bit time measurement 1 0 bus arbitration 1 1 reserved / do not use
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 152 freescale semiconductor arun? arbiter counter running flag this read-only bit in dicates the arbiter counter is running. reset clears arun. 1 = arbiter counter running 0 = arbiter counter stopped arovfl? arbiter counter overflow bit this read-only bit indicates an arbiter counter ov erflow. clear arovfl by writing any value to sciactl. writing 0s to am1 and am0 resets the counter keeps it in this idle state. reset clears arovfl. 1 = arbiter counter overflow has occurred 0 = no arbiter counter overflow has occurred ard8? arbiter counter msb this read-only bit is the msb of the 9-bit arbiter c ounter. clear ard8 by writing any value to sciactl. reset clears ard8. 13.9.2 esci arbite r data register ard7?ard0 ? arbiter least significant counter bits these read-only bits are the eight lsbs of the 9-bi t arbiter counter. clear ard7?ard0 by writing any value to sciactl. writing 0s to am1 and am0 permanent ly resets the counter and keeps it in this idle state. reset clears ard7?ard0. 13.9.3 bit time measurement two bit time measurement modes, described here, are available acco rding to the state of aclk. 1. aclk = 0 ? the counter is clock ed with one quarter of the bus clock. the counter is started when a falling edge on the rxd pin is detected. the counter will be stopped on the next falling edge. arun is set while the counter is running, afin is set on the second falling edge on rxd (for instance, the counter is stopped). this mode is used to recover the received baud rate. see figure 13-20 . 2. aclk = 1 ? the counter is clocked with one quarter of the esci input clock generated by the esci prescaler. the counter is started when a logic 0 is detected on rxd (see figure 13-21 ). a logic 0 on rxd on enabling the bit time measurement wi th aclk = 1 leads to immediate start of the counter (see figure 13-22 ). the counter will be stopped on the nex t rising edge of rxd. this mode is used to measure the length of a received break. 13.9.4 arbitration mode if am[1:0] is set to 10, the arbiter module operates in arbitration mode. on every rising edge of sci_txd (output of the esci module, internal chip signal), the counter is started. when the counter reaches $38 (aclk = 0) or $08 (aclk = 1), rxd is statically sensed. if in this case, rxd is sensed low (for example, address: $0019 bit 7654321bit 0 read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 = unimplemented figure 13-19. esci arbiter data register (sciadat)
esci arbiter mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 153 another bus is driving the bus dominant) alost is se t. as long as alost is set, the txd pin is forced to 1, resulting in a seized transmission. if sci_txd is sensed logic 0 without having sensed a logic 0 before on rxd, the counter will be reset, arbitration operation will be restarted after the next rising edge of sci_txd. figure 13-20. bit time measurement with aclk = 0 figure 13-21. bit time measurement with aclk = 1, scenario a figure 13-22. bit time measurement with aclk = 1, scenario b cpu writes sciactl counter starts, counter stops, measured time cpu reads result rxd with $20 arun = 1 afin = 1 out of sciadat cpu writes sciactl with $30 counter starts, arun = 1 counter stops, afin = 1 measured time cpu reads result out rxd of sciadat cpu writes sciactl counter starts, counter stops, measured time cpu reads result rxd out of sciadat afin = 1 arun = 1 with $30
enhanced serial communicatio ns interface (esci) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 154 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 155 chapter 14 system integration module (sim) 14.1 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. the sim is a system state controll er that coordinates the central processor unit (cpu) and exception timing. together with the cpu, the sim controls all microcontroller unit (mcu) activities. a block diagram of the sim is shown in figure 14-1 . the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 14-1 shows the internal signal names used in this section. 14.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 14-2 . this clock originates from either an external oscillat or or from the internal clock generator. table 14-1. signal name conventions signal name description cgmxclk selected clock source from internal clock generator module (icg) cgmout clock output from icg module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset (por) module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 156 freescale semiconductor figure 14-1. sim block diagram figure 14-2. system clock signals stop/wait clock control clock generators por control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to icg) cgmout (from icg) internal clocks master reset control lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from icg) 2 forced mon mode entry (from menrst module) icg cgmxclk 2 bus clock generators sim icg sim counter monitor mode clock select circuit iclk cs 2 a b s* cgmout * when s = 1, cgmout = b user mode generator eclk
reset and system initialization mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 157 14.2.1 bus timing in user mode , the internal bus frequency is the internal clock generator output (cgmxclk) divided by four. 14.2.2 clock startup fr om por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals ar e inactive and held in an inactive phase until after 4096 cgmxclk cycles. the mcu is held in reset by the sim during this entire period. the bus clocks start upon completion of the timeout. 14.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or rese t, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become ac tive until after the stop delay timeout. stop mode recovery timing is discussed in detail in 14.6.2 stop mode . in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 14.3 reset and s ystem initialization the mcu has these internal reset sources: power-on reset (por) module computer operating properly (cop) module low-voltage inhibit (lvi) module illegal opcode illegal address forced monitor mode entr y reset (menrst) module all of these resets produce the vector $fffe?$ffff ($fefe?$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. these internal resets clear the sim counter and set a corresponding bit in the sim reset status register (srsr). see 14.4 sim counter and 14.7.2 sim reset status register . 14.3.1 external pin reset the rst pin circuits include an internal pul lup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t irl time. figure 14-3 shows the relative timing. figure 14-3. external reset timing rst iab pc vect h vect l cgmout
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 158 freescale semiconductor 14.3.2 active resets from internal sources an internal reset can be caused by an illegal addr ess, illegal opcode, cop timeout, lvi, por, or menrst as shown in figure 14-4 . note for lvi or por resets, the sim c ycles through 4096 cgmxclk cycles during which the sim asserts irst. the internal reset signal then follows with the 64-cycle phase as shown in figure 14-5 . the cop reset is asynchronous to the bus clock. figure 14-4. sources of internal reset figure 14-5. internal reset timing 14.3.2.1 power-on reset when power is first applied to the mcu, the power- on reset (por) module generates a pulse to indicate that power-on has occurred. the mcu is held in reset while the sim counter counts out 4096 cgmxclk cycles. another 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the internal clock generator. the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. table 14-2. reset recovery timing reset type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) illegal address reset illegal opcode reset cop reset lvi por internal reset menrst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk
reset and system initialization mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 159 figure 14-6. por recovery 14.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the reset status register (srsr). to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12?5 of the sim counter. the sim counter output, which occurs at least every 4080 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high-voltage signal on the irq pin. this prevents the cop from becoming disabled as a result of external noise. 14.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the configuration register (config1) is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. 14.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. 14.3.2.5 forced monitor mode entry reset (menrst) the menrst module is monitoring the reset vector fetc hes and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode. see 19.3 monitor module (mon) . porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles $fffe $ffff
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 160 freescale semiconductor 14.3.2.6 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v tripf voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwrd and lvirstd bits in the config register are at 0. the mcu is held in reset until v dd rises above v tripr. the mcu remains in reset until the sim counts 4096 cgmxclk to begin a reset recovery. another 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. see chapter 11 low-voltage inhibit (lvi) module . 14.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly mo dule (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clock ed by the falling edge of cgmxclk. 14.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the internal clock generator to drive the bus clock state machine. 14.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt or reset, the sim senses the state of t he short stop recovery bit, ssrec, in the configuration register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. 14.4.3 sim counter and reset states the sim counter is free-running after all reset states. see 14.3.2 active resets from internal sources for counter control and internal reset recovery sequences. 14.5 program exception control normal, sequential program execution can be changed in two ways: 1. interrupts a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset
program exception control mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 161 14.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the return-from-interrupt (rti) instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 14-7 shows interrupt entry timing. figure 14-8 shows interrupt recovery timing. figure 14-7 . interrupt entry figure 14-8. interrupt recovery interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. as shown in figure 14-9 , once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the i bit is cleared. module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 162 freescale semiconductor figure 14-9. interrupt processing 14.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. no no no yes no yes no yes yes from reset i bit set? irq interrupt icg clk mon interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes i bit set? yes other interrupts no swi instruction rti instruction ? ? ? ? ?
program exception control mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 163 if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 14-10 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the load-accumulator- from-memory (lda) instruction is executed. figure 14-10 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805, m146805, and mc68hc05 families the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 14.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 14.5.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 164 freescale semiconductor 14.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. see 19.2 break module (brk) . the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 14.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 14.6 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. low-power modes are exited via an interrupt or reset. 14.6.1 wait mode in wait mode, the cpu clocks ar e inactive while one set of peripheral clocks continues to run. figure 14-11 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset. if the cop di sable bit, copd, in the configuration register is 0, then the computer operating properly module (c op) is enabled and remains active in wait mode. figure 14-11. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction.
low-power modes mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 165 figure 14-12 and figure 14-13 show the timing for wait recovery. figure 14-12. wait recovery from interrupt figure 14-13. wait recovery from internal reset 14.6.2 stop mode in stop mode, the sim counter is held in reset and the cpu and peripheral clocks are held inactive. if the stoposcen bit in the configuration register is not enabled, the sim also disables the internal clock generator module outputs (cgmout and cgmxclk). the cpu and peripheral clocks do not become acti ve until after the stop delay timeout. stop mode is exited via an interrupt request from a module that is still active in stop mode or from a system reset. an interrupt request from a module that is still active in stop mode can cause an exit from stop mode. stop recovery time is selectable using the ssrec bit in the configuration register. if ssrec is set, stop recovery is reduced from the normal delay of 4096 cg mxclk cycles down to 32. stacking for interrupts begins after the selected stop recovery time has elapsed. when stop mode is exited due to a reset condition, th e sim forces a long stop recovery time of 4096 cgmxclk cycles. note short stop recovery is ideal for applicat ions using canned oscillators that do not require long startup times for stop mode. external crystal applications should use the full stop recovery time by clearing the ssrec bit. the sim counter is held in reset from the executi on of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 14-14 shows stop mode entry timing. $de0c $de0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $de $a6 iab idb exitstopwait note: exitstopwait = cpu interrupt iab idb irst $a6 $a6 $de0b rst vct h rst vct l $a6 cgmxclk 64 cycles
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 166 freescale semiconductor figure 14-14. stop mode entry timing figure 14-15. stop mode recovery from interrupt 14.7 sim registers the sim has three memory mapped registers. table 14-3 shows the mapping of these registers. 14.7.1 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caus ed an exit from stop or wait mode. table 14-3. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset:00000000 r= reserved note: 1. writing a 0 clears sbsw figure 14-16. sim break status register (sbsr) stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
sim registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 167 sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 14.7.2 sim reset status register this register contains seven bits that show the sour ce of the last reset. the status register will clear automatically after reading it. a power-on reset sets t he por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin rst 0 = por or read of spsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr menrst ? forced monitor mode entry reset bit 1 = last reset was caused by the menrst circuit 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad menrst lvi 0 write: por:10000000 = unimplemented figure 14-17. sim reset status register (srsr)
system integration module (sim) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 168 freescale semiconductor 14.7.3 sim break flag control register the sim break flag control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset:00000000 r= reserved figure 14-18. sim break flag control register (sbfcr)
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 169 chapter 15 serial peripheral interface (spi) module 15.1 introduction this section describes the serial peripheral interfac e (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 15.2 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts with cpu service: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated circuit) compatibility 15.3 pin name and regi ster name conventions the generic names of the spi input/output (i/o) pins are: ss (slave select) spsck (spi serial clock) mosi (master out slave in) miso (master in slave out) the spi shares four i/o pins with a parallel i/o port. the full name of an spi pin reflects the name of the shared port pin. table 15-1 shows the full names of the spi i/o pins. the generic pin names appear in the text that follows. table 15-1. pin name conventions spi generic pin name miso mosi ss spsck full spi pin name ptc0/miso ptc1/mosi pta6/ss pta5/spsck
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 170 freescale semiconductor figure 15-1. block diagram highlighting spi block and pins the generic names of the spi i/o registers are: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) table 15-2 shows the names and the addresses of the spi i/o registers. single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 171 15.4 functional description figure 15-2 shows the structure of the spi module. figure 15-2. spi module block diagram table 15-2. i/o register addresses register name address spi control register (spcr) $000d spi status and control register (spscr) $000e spi data register (spdr) $000f transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus bus clock modfen errie control modf spmstr mosi miso spsck ss
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 172 freescale semiconductor the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. all spi interrupts can be serviced by the cpu. the following paragraphs describe the operation of the spi module. 15.4.1 master mode the spi operates in master mode when the spi master bit, spmstr (spcr $0010), is set. note configure the spi modules as mast er and slave before enabling them. enable the master spi before enabling t he slave spi. disable the slave spi before disabling the master spi. see 15.13.1 spi control register . figure 15-3. full-duplex master-slave connections only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte (spscr $0011). the byte begins shifting out on the mosi pin under the control of the serial clock. (see table 15-3 ). the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 15.13.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends wh en the receiver full bit, sprf (spscr), becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears spr f by reading the spi status and control register and then reading the spi data register. writing to the spi data register clears the sptie bit. 15.4.2 slave mode the spi operates in slave mode when the spmstr bi t (spcr, $0010) is clear. in slave mode the spsck pin is the input for the serial cl ock from the master mcu. before a data transmission occurs, the ss pin of the slave mcu must be at logic 0. ss must remain low until the tr ansmission is complete. (see 15.6.2 mode fault error .) shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
transmission formats mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 173 in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it is transferred to the receive data register, and the sprf bit (spscr) is set. to prev ent an overflow condition, slave software then must read the spi data register before another byte enters the shift register. the maximum frequency of the spsck for an spi confi gured as a slave is the bus clock speed, which is twice as fast as the fastest master spsck clock that can be generated. the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 15.5 transmission formats .) if the write to the data register is late, the spi transm its the data already in the shift register from the previous transmission. note to prevent spsck from appearing as a clock edge, spsck must be in the proper idle state before the slave is enabled. 15.5 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock line synchronizes shifti ng and sampling on the two serial data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi dev ice, the slave select line can be used optionally to indicate a multiple-master bus contention. 15.5.1 clock phase and polarity controls software can select any of four combinations of seri al clock (sck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signifi cant effect on the transmission format. the clock phase (cpha) control bit (spcr) select s one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the pha se and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note before writing to the cpol bit or the cpha bit (spcr), disable the spi by clearing the spi enable bit (spe).
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 174 freescale semiconductor 15.5.2 transmission format when cpha = 0 figure 15-4 shows an spi transmission in which cpha ( spcr) is 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), an d master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi (see 15.6.2 mode fault error ). when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the fi rst spsck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low again between each byte transmitted. figure 15-4. transmission format (cpha = 0) 15.5.3 transmission format when cpha = 1 figure 15-5 shows an spi transmission in which cpha ( spcr) is 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), an d master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 15.6.2 mode fault error .) when cpha = 1, the master begins drivi ng its mosi pin on the first spsck edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferabl e in systems having only one master and only one slave driving the miso data line. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol = 1 mosi from master miso from slave ss to slave capture strobe
transmission formats mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 175 figure 15-5. transmission format (cpha = 1) 15.5.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), transmissions are started by a software write to the spdr ($0012). cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sck signal. when cpha = 0, the sck si gnal remains inactive for the first half of the first sck cycle. when cpha = 1, the first sck cycle begins with an edge on the sck line from its inactive to its active level. the spi clock rate (selected by spr1?spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 15-6 .) the internal spi clock in the master is a free-running derivative of the inter nal mcu clock. it is only enabled when both the spe and spmstr bits (spcr) are set to conserve power. sck edges occur half way through the low time of the internal mcu clock. since the spi clock is free-running, it is unce rtain where the write to the spdr will occur relative to the slower sck. this uncertainty causes t he variation in the initiation delay shown in figure 15-6 . this delay will be no longer than a single spi bit time. that is, the maximum delay between the write to spdr and the start of the spi transmission is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol =1 mosi from master miso from slave ss to slave capture strobe
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 176 freescale semiconductor figure 15-6. transmission start delay (master) 15.6 error conditions two flags signal spi error conditions: 1. overflow (ovrf in spscr) ? faili ng to read the spi data register bef ore the next byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the spi data register. ovrf is in the spi status and control register. 2. mode fault error (modf in spscr) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. mo df is in the spi status and control register. write to spdr initiation delay bus mosi sck cpha = 1 sck cpha = 0 sck cycle number msb bit 6 12 clock write to spdr earliest latest sck = internal clock 2; earliest latest 2 possible start points sck = internal clock 8; 8 possible start points earliest latest sck = internal clock 32; 32 possible start points earliest latest sck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? ? ? initiation delay from write spdr to transfer begin
error conditions mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 177 15.6.1 overflow error the overflow flag (ovrf in spscr) becomes set if t he spi receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next tr ansmission occurs. (see figure 15-4 and figure 15-5 .) if an overflow occurs, the data bei ng received is not transferred to the receive data register so that the unread data can still be read. therefore, an overflow error always indicates the loss of data. ovrf generates a receiver/error cp u interrupt request if the error in terrupt enable bit (errie in spscr) is also set. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 15-9 .) it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if an end-of-block transmission interrupt was meant to pull the mcu out of wait, having an overflow condition without overflow interr upts enabled causes the mcu to hang in wait mode. if the ovrf is enabled to generate an interrupt, it can pull the mcu out of wait mode instead. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 15-7 shows how it is possi ble to miss an overflow. figure 15-7. missed read of overflow condition the first part of figure 15-7 shows how to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf flag can be set in between the time that spscr and spdr are read. in this case, an overflow can be easily missed. since no more sprf interrupts can be generated until this ovrf is serviced, it will not be obvious that bytes ar e being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr after the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions will comple te with an sprf interrupt. figure 15-8 illustrates this pr ocess. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit (spscr). read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set and ovrf bit clear. cpu reads byte 1 in spdr, clearing sprf bit. byte 2 sets sprf bit. cpu reads spscrw with sprf bit set and ovrf bit clear. byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, but not ovrf bit. byte 4 fails to set sprf bit because ovrf bit is set. byte 4 is lost. 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 178 freescale semiconductor figure 15-8. clearing sprf when ovrf interrupt is not enabled 15.6.2 mode fault error for the modf flag (in spscr) to be set, the mode fault error enable bit (modfen in spscr) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 15-9 ). it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. figure 15-9. spi interrupt request generation read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set and ovrf bit clear. cpu reads byte 1 in spdr, clearing sprf bit. cpu reads spscr again to check ovrf bit. byte 2 sets sprf bit. cpu reads spscr with sprf bit set and ovrf bit clear. byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit. cpu reads spscr again to check ovrf bit. cpu reads byte 2 spdr, clearing ovrf bit. byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, clearing sprf bit. cpu reads spscr again to check ovrf bit. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 spi receive complete spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request
error conditions mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 179 in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all data direction register (ddr ) bits associated with the spi shared port pins. note setting the modf flag (spscr) does not clear the spmstr bit. reading spmstr when modf = 1 will indicate a mode fault error occurred in either master mode or slave mode. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once t he incoming spsck returns to its idle level after the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level after the shift of the last data bit. (see 15.5 transmission formats .) note when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later deselected (ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then late r deselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bi t or reset the spi in any way. software can abort the spi transmission by toggling the spe bit of the slave. note a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if a transmission has begun. to clear the modf flag, read the spscr and then wr ite to the spcr register. this entire clearing procedure must occur with no modf condition existing or else the flag will not be cleared.
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 180 freescale semiconductor 15.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests: the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests. the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt, provided that the spi is enabled (spe = 1). the error interrupt enable bit (errie) enables both the modf and ovrf flags to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf flag is enabled to generate receiver/error cpu interrupt requests. two sources in the spi status and control register can generate cpu interrupt requests: 1. spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate an spi receiver/error cpu interrupt request. 2. spi transmitter empty (spte) ? the spte bit becom es set every time a by te transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate an spte cpu interrupt request. 15.8 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag ( spte in spscr) indicates when the transmit data buffer is ready to accept new data. write to the spi data register only when the spte bit is high. figure 15-10 shows the timing associated wi th doing back-to-back transmissi ons with the spi (spsck has cpha:cpol = 1:0). for a slave, the transmit data buffer allows back-to-b ack transmissions to occur without the slave having to time the write of its data between the transmissions. also, if no new data is written to the data buffer, the last value contained in the shift regi ster will be the next data word transmitted. table 15-3. spi interrupts flag request spte (transmitter empty) spi transmi tter cpu interrupt request (sptie = 1) sprf (receiver full) spi receiver cpu interrupt request (sprie = 1) ovrf (overflow) spi receiver/error interrupt request (sprie = 1, errie = 1) modf (mode fault) spi receiver/error interr upt request (sprie = 1, errie = 1, modfen = 1)
resetting the spi mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 181 figure 15-10. sprf/spte cpu interrupt timing 15.9 resetting the spi any system reset completely resets the spi. partia l reset occurs whenever th e spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaul ted back to being general-purpose i/o. the following additional items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr regist er (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to reset all control bits when spe is set back to high fo r the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing a 0 to the spe bit. the spi also can be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. bit 3 mosi spsck (cpha:cpol = 1:0) spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing byte 1 transfers from transmit data 3 1 2 2 3 5 spte bit. register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set.
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 182 freescale semiconductor 15.10 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 15.10.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode, the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occu rs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). (see 15.7 interrupts .) 15.10.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after the mcu exits stop mode. if stop mode is exited by reset, any transfer in progress is aborted and the spi is reset. 15.11 spi during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr, $fe03) enables software to clear status bits during the break state. (see 19.2.1.1 flag protection during break interrupts .) to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the data register in break mode will not initiate a transmission nor will this data be transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 15.12 i/o signals the spi module has four i/o pins and shares three of them with a parallel i/o port. miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select v ss ? clock ground
i/o signals mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 183 the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 15.12.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmit serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port. 15.12.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmit serial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. 15.12.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 15.12.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 15.5 transmission formats .) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low throughout the transmission for the cpha = 1 format. see figure 15-11 . figure 15-11. cpha/ss timing byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 184 freescale semiconductor when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 15.13.2 spi status and control register .) note a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if a transmission already has begun. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 15.6.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the data register. (see table 15-4 .) 15.12.5 v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize r adio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin. 15.13 i/o registers three registers control and monitor spi operation: spi control register (spcr $0010) spi status and control register (spscr $0011) spi data register (spdr $0012) 15.13.1 spi control register the spi control register: enables spi module interrupt requests selects cpu interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module table 15-4. spi configuration spe spmstr modfen spi conf iguration state of ss logic 0 x x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi x = don?t care
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 185 sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the sh ift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 15-4 and figure 15-5 .) to transmit data between spi modules, the spi modules must have identical cpol bits. reset clears the cpol bit. cpha ? clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 15-4 and figure 15-5 .) to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 15-11 ). reset sets the cpha bit. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss . any data written after the falling edge is stored in the dat a register and transferred to the shift register at the current transmission. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set. (see 15.6.2 mode fault error ). a logic 1 on the ss pin does not in any way affect the state of the spi state machine. spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins address: $000d bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 15-12. spi control register (spcr)
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 186 freescale semiconductor spe ? spi enable bit this read/write bit enables the spi module. clear ing spe causes a partial reset of the spi (see 15.9 resetting the spi ). reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie ? spi transmit interrupt enable bit this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 15.13.2 spi status and control register the spi status and control register contai ns flags to signal t he following conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also c ontains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. any read of the spi data register clears the sprf bit. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read-only bit enables the modf and ovrf flags to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests address: $000e bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 15-13. spi status and control register (spscr)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 187 ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and t hen reading the spi data register. reset clears the ovrf flag. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission. in a master spi, the modf flag is set if the ss pin goes low at any time. clear the modf bit by reading the spi status and control register with modf set and then writing to the spi data register. reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note do not write to the spi data register unless the spte bit is high. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since t he transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already ac tive slave, the load of the shift register cannot occur until the transmission is completed. this impl ies that a back-to-back write to the transmit data register is not possible. the spte i ndicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not av ailable as a general pur pose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-pu rpose i/o regardless of the value of modfen. (see 15.12.4 ss (slave select) ). if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 15.6.2 mode fault error ).
serial peripheral in terface (spi) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 188 freescale semiconductor spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 15-5 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the inte rnal clock generator module (icg), see chapter 8 internal clock generator (icg) module . bd = baud rate divisor 15.13.3 spi data register the spi data register is the read/write buffer for the receive data register and the transmit data register. writing to the spi data register writes data into the transmit data register. r eading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate buffers that can contain different values. see figure 15-2 r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the buffer read is not the same as the buffer written. table 15-5. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 address: $000f bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 15-14. spi data register (spdr) baud rate cgmout 2bd -------------------------- =
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 189 chapter 16 timebase module (tbm) 16.1 introduction this section describes the timebase module (tbm). the tbm will generate periodic interrupts at user selectable rates using a counter clocked by either the in ternal or external clock sources. this tbm version uses 15 divider stages, eight of which are user selectable. note the tbm on this device differs from that of the mc68hc908kx8 in that it has an additional divide-by-128 at the front end of the divider chain. for further information regarding timers on m68hc08 family devices, please consult the hc08 timer reference manual , freescale order number tim08rm/ad. 16.2 features features of the tbm module include: software configurable periodic interrupts with divide-by-1024, 2048, 4096, 8192, 16384, 262144, 1048576, and 4194304 taps of the selected clock source configurable for operation during stop mode to allow periodic wake up from stop 16.3 functional description this module can generate a periodic interrupt by dividing the clock source supplied from the internal clock generator module, tbmclk. note that this clock sour ce is the external clock eclk when the ecgon bit in the icg control register (icgcr) is set. otherwise , tbmclk is driven at the internally generated clock frequency (iclk). in other words, if the external clock is enabled it will be used as the tbmclk, even if the mcu bus clock is based on the internal clock. the counter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 16-1 , starts counting when the tbon bit is set. when the counter ov erflows at the tap selected by tbr2?tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu. the tbif flag is cleared by writing a 1 to the tack bit. the first time the tbif flag is set after enabling the timebase module, the interrupt is generated at approximately half of the ov erflow period. subsequent events occur at the exact period. the timebase module may remain active after execution of the stop instruction if the internal clock generator has been enabled to operate during stop mode through the osceninstop bit in the configuration register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode.
timebase module (tbm) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 190 freescale semiconductor figure 16-1. timebase block diagram 16.4 interrupts the timebase module can periodically interrupt the cpu with a rate defined by the selected tbmclk and the select bits tbr2?tbr0. when the timebase counter c hain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the c ounter chain overflow will generate a cpu interrupt request. interrupts must be acknowledged by writing a 1 to the tack bit. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbmint tbon 2 r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 0 1 tmbclksel from config2 tbmclk from icg module divide by 128 prescaler
tbm interrupt rate mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 191 16.5 tbm interrupt rate the interrupt rate is determined by the equation: where: f tbmclk =frequency supplied from the inte rnal clock generator (icg) module divider = divider value as det ermined by tbr2?tbr0 settings. see table 16-1 as an example, a clock source of 4.9152 mhz and th e tbr2?tbr0 set to {011}, the divider tap is 128 and the interrupt rate calculates to 128/4.9152 x 10 6 = 26 s. 16.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.6.1 wait mode the timebase module remains active after execution of the wait instruction. in wait mode the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before executing the wait instruction. 16.6.2 stop mode the timebase module may remain active after execution of the stop instruction if the internal clock generator has been enabled to operate during stop mode through the osceninstop bit in the configuration register. the timebase module can be used in this mode to generate a periodic wake up from stop mode. table 16-1. timebase divider selection tbr2 (1) 1. do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). tbr1 (1) tbr0 (1) divider tap tmbclksel 01 0 0 0 32,768 4,194,304 0 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 111 8 1024 t tbmrate 1 f tbmrate ------------------------ divider f tbmclk -------------------- - ==
timebase module (tbm) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 192 freescale semiconductor if the internal clock generator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the ti mebase register is not accessible by the cpu. if the timebase functions are not required during stop mode, reduce power consumption by disabling the timebase module before execut ing the stop instruction. 16.7 timebase control register the timebase has one register, the timebase control register (tbcr), which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag this read-only flag bit is set when th e timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending tbr2?tbr0 ? timebase divider selection bits these read/write bits select the tap in the counter to be used for timebase interrupts as shown in table 16-1 . note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). tack? timebase acknowledge bit the tack bit is a write-only bit and always reads as 0. writing a 1 to this bit clears tbif, the timebase interrupt flag bit. writing a 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled bit this read/write bit enables the timebase interrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt is enabled. 0 = timebase interrupt is disabled. tbon ? timebase enabled bit this read/write bit enables the timebase. timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialized by clearing and then setting this bit. reset clears the tbon bit. 1 = timebase is enabled. 0 = timebase is disabled and t he counter initialized to 0s. note clearing tbon has no effect on the tbif flag. address: $001c bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 = unimplemented r = reserved figure 16-2. timebase control register (tbcr)
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 193 chapter 17 timer interface a (tima) module 17.1 introduction this section describes the timer interface a module (t ima). the tima is a 2-channel timer that provides a timing reference with input capture, output comp are, and pulse width modulation (pwm) functions. figure 17-2 is a block diagram of the tima. for further information regarding timers on m68hc08 family devices, please consult the hc08 timer reference manual , freescale document order number tim08rm/ad. 17.2 features features include: two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pwm signal generation programmable tima clock input ? 7-frequency internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow tima counter stop and reset bits 17.3 functional description figure 17-2 shows the tima structure. the central component of the tima is the 16-bit tima counter that can operate as a free-running counter or a modulo up-counter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh?tamodl, control the modulo value of the tima counter. software can read the tima counter value at any time without affecting the counting sequence. the two tima channels are programmable independently as input capture or output compare channels.
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 194 freescale semiconductor figure 17-1. block diagram highlighting tima block and pins single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 195 figure 17-2. tima block diagram 17.3.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tima status and control register select the tima clock source. 17.3.2 input capture an input capture function has thr ee basic parts: edge select logic, an input capture latch, and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the correspondi ng input capture edge detector senses a defined transition. the polarity of the active edge is programma ble. the level transition which triggers the counter transfer is defined by the corresponding input ed ge bits (elsxb and elsxa in tasc0 through tasc1 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the tima latches the contents of the tima counter into the tima channel registers, tachxh?tachxl. input captures can generate tima cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture in terrupts or by polling the status flag bit. the free-running counter contents are transferred to the tima channel status and control register (tachxh?tachxl, see 17.8.5 tima channel registers ) on each proper signal transition regardless of whether the tima channel flag (ch0f?ch1f in tasc0?tasc 1 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register 2 bus cycles after the actual event prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tach0h:tach0l ms0a els0b els0a ptd0 tof toie inter- channel 0 tamodh:tamodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptd0/tach0 ptd1/tach1 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tach1h:tach1l ms1a els1b els1a ptd1 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 196 freescale semiconductor occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a perio d, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establis h a time reference. in this case, an input capture function is used in conjuncti on with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 17.8.5 tima channel registers ). because both input captures and output compares are refer enced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture channel register (tachxh?tachxl). 17.3.3 output compare with the output compare function, the tima can gener ate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tima can set, clear, or toggle the channel pin. output compares can generate tima cpu interrupt requests. 17.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 17.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tima over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tima may pass the new value before it is written. use these methods to synchronize unbuffered ch anges in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current counter overflow period. writing a larg er value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 197 17.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the ptd0/tach0 pin. the tima channel registers of the linked pair alternately control the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 registers initially controls the output on the ptd0/tach0 pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, ptd1 /tach1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 17.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between overflows is the period of the pwm signal. as figure 17-3 shows, the output compare value in the ti ma channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tima to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tima to set the pin if the state of the pwm pulse is logic 0. figure 17-3. pwm period and pulse width ptdx/tchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 198 freescale semiconductor the value in the tima counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tima counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 17.8.1 tima status and control register ). the value in the tima channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 incremen ts. writing $0080 (128) to the tima channel registers produces a duty cycle of 128/256 or 50%. 17.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 17.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the tima channel registers. an unsynchronized write to the tima channel regi sters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tima overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tima may pass the new value before it is written to the tima channel registers. use these methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable ti ma overflow interrupts and write the new value in the tima overflow interrupt routine. the tima ov erflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 17.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the ptd0/tach0 pin. the tima channel registers of the li nked pair alternately control the pulse width of the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the ptd0/tach0 pin. writing to the tima channel 1 registers enables the tima cha nnel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pulse width are the ones wri tten to last. tasc0 controls and monitors the buffered
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 199 pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, ptd1/tach1, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 17.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by setting the tima stop bit, tstop. b. reset the tima counter prescaler by setting the tima reset bit, trst. 2. in the tima counter modulo registers (tamodh?tamodl), write the value for the required pwm period. 3. in the tima channel x registers (tachxh?tachxl), write the value for the required pulse width. 4. in tima channel x status and control register (tascx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb?msxa. see table 17-2 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 17-2 . note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima status control register (tasc), clear the tima stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tima channel 0 registers (tach0h?tach0l) initially control the buffered pwm output. tima status control register 0 (tasc0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 17.8.4 tima channel status and control registers .
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 200 freescale semiconductor 17.4 interrupts these tima sources can generate interrupt requests: tima overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. to f and toie are in the tima status and control register. tima channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tima cpu inte rrupt requests are controlled by the channel x interrupt enable bit, chxie. 17.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 17.5.1 wait mode the tima remains active after the execution of a wait instruction. in wait mode, the tima registers are not accessible by the cpu. any enabled cpu interrupt request from the tima can bring the mcu out of wait mode. if tima functions are not required during wait mode , reduce power consumption by stopping the tima before executing the wait instruction. 17.5.2 stop mode the tima is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tima counter. tima operation resumes when the mcu exits stop mode. 17.6 tima during break interrupts a break interrupt stops the tima c ounter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit.
i/o signals mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 201 17.7 i/o signals port d shares two of its pins with the tima. there is no external clock input to the tima prescaler. the two tima channel i/o pins are ptd0/tach0 and ptd1/tach1. see chapter 12 input/output (i/o) ports (ports) 17.7.1 tima channel i/o pins (ptd0/tach0, ptd1/tach1) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptd0/tach0 and ptd1/tach1 can be configured as buffered output compare or buffered pwm pins. 17.8 i/o registers these i/o registers control and monitor tima operation: tima status and control register, tasc tima control registers, tacnth?tacntl tima counter modulo registers, tamodh?tamodl tima channel status and control registers, tasc0 and tasc1 tima channel registers, tach0h?tach0l and tach1h?tach1l 17.8.1 tima status and control register the tima status and control register (tasc): enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock tof ? tima overflow flag bit this read/write flag is set when the tima counter reaches the modulo value programmed in the tima counter modulo registers. clear tof by reading t he tima status and control register when tof is set and then writing a 0 to tof. if another tima overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = tima counter has reached modulo value 0 = tima counter has not reached modulo value address: $0020 bit 7654321bit 0 read: tof toie tstop 0 r ps2 ps1 ps0 write: 0 trst reset:00100000 r= reserved figure 17-4. tima status and control register (tasc)
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 202 freescale semiconductor toie ? tima overflow interrupt enable bit this read/write bit enables tima overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ? tima stop bit this read/write bit stops the tima counter. countin g resumes when tstop is cleared. reset sets the tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note do not set the tstop bit before entering wait mode if the tima is required to exit wait mode. also, when the tstop bit is set and the timer is configured for input capture operation, input captures are inhibited until tstop is cleared. when using tstop to stop the timer counter, check for any timer flags being set. if a timer flag is set, it must be cleared by clearing tstop, then clearing the flag, then setting tstop again. trst ? tima reset bit setting this write-only bit resets the tima counter and the tima prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tima counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tima counter as table 17-1 shows. reset clears the ps[2:0] bits. table 17-1. prescaler selection ps[2:0] tima clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 unused
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 203 17.8.2 tima c ounter registers the two read-only tima counter registers contain the high and low bytes of the value in the tima counter. reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears the tima counter registers. note if tacnth is read during a break interrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. 17.8.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the modulo value, the overflow flag (tof) becomes set, and the tima counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is wri tten. reset sets the tima counter modulo registers. note reset the tima counter before writing to the tima counter modulo registers. register name and address tacnth ? $0021 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address tacntl ? $0022 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 r= reserved figure 17-5. tima counter registers (tacnth and tacntl) register name and address tamodh ? $0023 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address tamodl ? $0024 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 17-6. tima counter modulo registers (tmodh and tmodl)
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 204 freescale semiconductor 17.8.4 tima channel stat us and control registers each of the tima channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tima overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tima counter registers matches the value in the tima channel x registers. when chxie = 1, clear chxf by reading tima channel x status and control register with chxf set, and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tima cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tima channel 0. register name and address tasc0 ? $0025 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address tasc1 ? $0028 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 rr = reserved figure 17-7. tima channel status and control register (tasc0?tasc1)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 205 setting ms0b disables the channel 1 status and control register and reverts tach1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 17-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin once pwm, input capture, or output compare operation is enabled (see table 17-2 ). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tima status and control register (tasc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port d, and pin ptd0/tach0 or pin ptd1/tach1 is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respective pin when pwm, input capture, or output compare mode is enabled. table 17-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note before enabling a tima channel register for input capture operation, make sure that the ptdx/tachx pin is stable for at least two bus clocks. table 17-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 206 freescale semiconductor tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/ write bit controls the behavior of the channel x output when the tima counter overflows. when ch annel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggle on tima counter overflow. note when tovx is set, a tima counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100 percent. as figure 17-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at 100 percent duty cycle level until the cycle after chxmax is cleared. note the pwm 100 percent duty cycle is defined as output high all of the time. to generate the 100 percent duty cycle, use the chxmax bit in the tscx register. the pwm 0 percent duty cycle is defined as output low all of the time. to generate the 0 percent duty cycle, select clear output on compare and then clear the tovx bit (chxmax = 0). figure 17-8. chxmax latency output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tov = 1 tov = 0
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 207 17.8.5 tima c hannel registers these read/write registers contain the captured tima counter value of the input capture function or the output compare value of the output compare function. the state of the tima channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures un til the low byte (tachxl) is read. in output compare mode (msxb?msxa 0:0), writing to the high byte of the tima channel x registers (tachxh) inhibits output compares and the chxf bit until the low byte (tachxl) is written. register name and address tach0h ? $0026 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach0l ? $0027 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tach1h ? $0029 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach1l ? $002a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 17-9. tima channel registers (tach0h/l?tach1h/l)
timer interface a (tima) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 208 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 209 chapter 18 timer interface b (timb) module 18.1 introduction this section describes the timer interface b module (t imb). the timb is a 2-channel timer that provides a timing reference with input capture, output comp are, and pulse width modulation (pwm) functions. figure 18-2 is a block diagram of the timb. for further information regarding timers on m68hc08 family devices, please consult the hc08 timer reference manual , freescale document order number tim08rm/ad. 18.2 features features include: two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pwm signal generation programmable timb clock input ? 7-frequency internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow timb counter stop and reset bits 18.3 functional description figure 18-2 shows the timb structure. the central component of the timb is the 16-bit timb counter that can operate as a free-running counter or a modulo up-counter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh?tbmodl, control the modulo value of the timb counter. software can read the timb counter value at any time without affecting the counting sequence. the two timb channels are programmable independently as input capture or output compare channels.
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 210 freescale semiconductor figure 18-1. block diagram highlighting timb block and pin single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 211 figure 18-2. timb block diagram 18.3.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the timb status and control register select the timb clock source. 18.3.2 input capture an input capture function has thr ee basic parts: edge select logic, an input capture latch, and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the correspondi ng input capture edge detector senses a defined transition. the polarity of the active edge is programma ble. the level transition which triggers the counter transfer is defined by the corresponding input ed ge bits (elsxb and elsxa in tbsc0 through tbsc1 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the timb latches the contents of the timb counter into the timb channel registers, tbchxh?tbchxl. input captures can generate timb cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture in terrupts or by polling the status flag bit. the free-running counter contents are transferred to the timb channel status and control register (tbchxh?tbchxl, see 18.8.5 timb channel registers ) on each proper signal transition regardless of whether the timb channel flag (ch0f?ch1f in tbsc0?tbsc 1 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register 2 bus cycles after the actual event prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tbch0h:tbch0l ms0a els0b els0a ptb6 tof toie channel 0 tbmodh:tbmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptb6/tbch0 ptb7/tbch1 logic 16-bit comparator 16-bit latch tbch1h:tbch1l ms1a els1b els1a ptb7 channel 1 tov1 ch1ie ch1f ch1max logic interrupt logic interrupt logic interrupt logic
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 212 freescale semiconductor occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a perio d, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establis h a time reference. in this case, an input capture function is used in conjuncti on with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 18.8.5 timb channel registers ). because both input captures and output compares are refer enced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture channel register (tbchxh?tbchxl). 18.3.3 output compare with the output compare function, the timb can gener ate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the timb can set, clear, or toggle the channel pin. output compares can generate timb cpu interrupt requests. 18.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 18.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a timb over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the timb may pass the new value before it is written. use these methods to synchronize unbuffered ch anges in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current counter overflow period. writing a larg er value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
functional description mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 213 18.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the ptb6/tbch0 pin. the timb channel registers of the linked pair alternately control the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 registers initially controls the output on the ptb6/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the output after the timb overflows. at each subsequent overflow, the timb channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptb7 /tbch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 18.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between overflows is the period of the pwm signal. as figure 18-3 shows, the output compare value in the ti mb channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the timb to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the timb to set the pin if the state of the pwm pulse is logic 0. figure 18-3. pwm period and pulse width the value in the timb counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the timb counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 18.8.1 timb status and control register ). the value in the timb channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 incremen ts. writing $0080 (128) to the timb channel registers produces a duty cycle of 128/256 or 50%. ptbx/tchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 214 freescale semiconductor 18.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 18.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the timb channel registers. an unsynchronized write to the timb channel regi sters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a timb overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the timb may pass the new value before it is written to the timb channel registers. use these methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable ti mb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb ov erflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 18.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the ptb6/tbch0 pin. the timb channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially cont rol the pulse width on the ptb6/tbch0 pin. writing to the timb channel 1 registers enables the timb cha nnel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at eac h subsequent overflow, the timb channel registers (0 or 1) that control the pulse width are the ones wri tten to last. tbsc0 controls and monitors the buffered pwm function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptb7/tbch1, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals.
interrupts mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 215 18.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by setting the timb stop bit, tstop. b. reset the timb counter prescaler by setting the timb reset bit, trst. 2. in the timb counter modulo registers (tbmodh?tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh?tbchxl), write the value for the required pulse width. 4. in timb channel x status and control register (tbscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb?msxa. see table 18-2 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 18-2 . note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb status control register (tbsc), clear the timb stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the timb channel 0 registers (tbch0h?tbch0l) initially control the buffered pwm output. timb status control register 0 (tbsc0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 18.8.4 timb channel status and control registers . 18.4 interrupts these timb sources can generate interrupt requests: timb overflow flag (tof) ? the tof bit is se t when the timb counter reaches the modulo value programmed in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt requests. to f and toie are in the timb status and control register. timb channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x timb cpu inte rrupt requests are controlled by the channel x interrupt enable bit, chxie.
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 216 freescale semiconductor 18.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 18.5.1 wait mode the timb remains active after the execution of a wait instruction. in wait mode, the timb registers are not accessible by the central processor unit (cpu). any enabled cpu interrupt request from the timb can bring the mcu out of wait mode. if timb functions are not required during wait mode , reduce power consumption by stopping the timb before executing the wait instruction. 18.5.2 stop mode the timb is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the timb counter. timb operation resumes when the mcu exits stop mode. 18.6 timb during break interrupts a break interrupt stops the timb c ounter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 18.7 i/o signals port b shares two of its pins with the timb. there is no external clock input to the timb prescaler. the two timb channel i/o pins are ptb6/tbch0 and ptb7/tbch1. see chapter 12 input/output (i/o) ports (ports) . 18.7.1 timb chan nel i/o pins (ptb7/tbch1?ptb6/tbch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptb6/tbch0 and ptb7/tbch1 can be configured as buffered output compare or buffered pwm pins.
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 217 18.8 i/o registers these i/o registers control and monitor timb operation: timb status and control register, tbsc timb control registers, tbcnth?tbcntl timb counter modulo registers, tbmodh?tbmodl timb channel status and control registers, tbsc0 and tbsc1 timb channel registers, tbch0h?tbch0l and tbch1h?tbch1l 18.8.1 timb status and control register the timb status and control register: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock tof ? timb overflow flag bit this read/write flag is set when the timb counter reaches the modulo value programmed in the timb counter modulo registers. clear tof by reading t he timb status and control register when tof is set and then writing a 0 to tof. if another timb overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = timb counter has reached modulo value 0 = timb counter has not reached modulo value toie ? timb overflow interrupt enable bit this read/write bit enables timb overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled address: $002b bit 7654321bit 0 read: tof toie tstop 0 r ps2 ps1 ps0 write: 0 trst reset:00100000 r= reserved figure 18-4. timb status and control register (tbsc)
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 218 freescale semiconductor tstop ? timb stop bit this read/write bit stops the timb counter. countin g resumes when tstop is cleared. reset sets the tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note do not set the tstop bit before entering wait mode if the timb is required to exit wait mode. also, when the tstop bit is set and the timer is configured for input capture operation, input captures are inhibited until tstop is cleared. when using tstop to stop the timer counter, check for any timer flags being set. if a timer flag is set, it must be cleared by clearing tstop, then clearing the flag, then setting tstop again. trst ? timb reset bit setting this write-only bit resets the timb counter and the timb prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the timb counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the timb counter as table 18-1 shows. reset clears the ps[2:0] bits. table 18-1. prescaler selection ps[2:0] timb clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 unused
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 219 18.8.2 timb c ounter registers the two read-only timb counter registers contain the high and low bytes of the value in the timb counter. reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears the timb counter registers. note if tbcnth is read during a break interrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. 18.8.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the modulo value, the overflow flag (tof) becomes set, and the timb counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is wri tten. reset sets the timb counter modulo registers. note reset the timb counter before writing to the timb counter modulo registers. register name and address tbcnth ? $002c bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address tbcntl ? $002d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 r= reserved figure 18-5. timb counter registers (tbcnth and tbcntl) register name and address tbmodh ? $002e bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address tbmodl ? $002f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 18-6. timb counter modulo registers (tmodh and tmodl)
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 220 freescale semiconductor 18.8.4 timb channel stat us and control registers each of the timb channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on timb overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the timb counter registers matches the value in the timb channel x registers. when chxie = 1, clear chxf by reading timb channel x status and control register with chxf set, and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables timb cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the timb channel 0. register name and address tbsc0 ? $0030 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address tbsc1 ? $0033 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 r= reserved figure 18-7. timb channel status and control registers (tbsc0?tbsc1)
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 221 setting ms0b disables the channel 1 status and control register and reverts tbch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 18-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin once pwm, input capture, or output compare operation is enabled. see table 18-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the timb status and control register (tbsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port b, and pin ptbx/tbchx is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respective pin when pwm, input capture, or output compare mode is enabled. table 18-2 shows how elsxb and elsxa work. re set clears the elsxb and elsxa bits. note before enabling a timb channel register for input capture operation, make sure that the ptbx/tbchx pin is stable for at least two bus clocks. table 18-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 222 freescale semiconductor tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggle on timb counter overflow. note when tovx is set, a timb counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100 percent. as figure 18-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at 100 percent duty cycle level until the cycle after chxmax is cleared. note the pwm 100 percent duty cycle is defined as output high all of the time. to generate the 100 percent duty cycle, use the chxmax bit in the tscx register. the pwm 0 percent duty cycle is defined as output low all of the time. to generate the 0 percent duty cycle, select clear output on compare and then clear the tovx bit (chxmax = 0). figure 18-8. chxmax latency output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tov = 1 tov = 0
i/o registers mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 223 18.8.5 timb c hannel registers these read/write registers contain the captured timb counter value of the input capture function or the output compare value of the output compare function. the state of the timb channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures un til the low byte (tbchxl) is read. in output compare mode (msxb?msxa 0:0), writing to the high byte of the timb channel x registers (tbchxh) inhibits output compares and the chxf bit until the low byte (tbchxl) is written. register name and address tbch0h ? $0031 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tbch0l ? $0032 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tbch1h ? $0034 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tbch1l ? $0035 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 18-9. timb channel registers (tbch0h/l?tbch1h/l)
timer interface b (timb) module mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 224 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 225 chapter 19 development support 19.1 introduction this section describes the break module, the mo nitor module (mon), and the monitor mode entry methods. 19.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features of the break module include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 19.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 19-2 shows the structure of the break module. when the internal address bus matches the value writt en in the break address registers or when software writes a 1 to the brka bit in the break status and c ontrol register, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode)
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 226 freescale semiconductor figure 19-1. block diagram highlighting brk and mon blocks the break interrupt timing is: when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 15,872 bytes 512 bytes 310 bytes 36 bytes
break module (brk) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 227 figure 19-2. break module block diagram by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routi ne, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 19.2.1.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag contro l register (sbfcr) enables software to clear status bits during the break state. see 14.7.3 sim break flag control register and the break interrupts subsection for each module. 19.2.1.2 tim during break interrupts a break interrupt stops the timer counter. 19.2.1.3 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 19.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (bscr) break address register high (brkh) break address register low (brkl) break status register (sbsr) break flag control register (sbfcr) address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim)
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 228 freescale semiconductor 19.2.2.1 break status and control register the break status and control register (bscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address re gister matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 19.2.2.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 19-3. break status and control register (bscr) address: $fe09 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 19-4. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 19-5. break address register low (brkl)
break module (brk) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 229 19.2.2.3 break status register the break status register (sbsr) contains a flag to indicate that a break caus ed an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 19.2.2.4 break flag control register the break control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 19.2.3 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. if enabled, the break module will remain enabled in wait and st op modes. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 19-6. break status register (sbsr) address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 19-7. break flag control register (sbfcr)
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 230 freescale semiconductor 19.3 monitor module (mon) the monitor module allows debugging and programmin g of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features of the monitor module include: normal user-mode pin functionality one pin dedicated to serial communi cation between mcu and host computer standard non-return-to-zero (nrz) communication with host computer standard communication baud rate (9600 @ 2.4576-mhz bus frequency) execution of code in random-a ccess memory (ram) or flash flash memory security feature (1) flash memory programming interface monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) normal monitor mode entry if v tst is applied to irq 19.3.1 functional description figure 19-8 shows a simplified diagram of the monitor mode. the monitor module receives and execut es commands from a host computer. figure 19-9 and figure 19-11 show example circuits used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer wh ile most mcu pins retain normal operating mode functions. all communicati on between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. table 19-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communication at 9600 baud provided one of the following sets of conditions is met: if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 9.8304 mhz (9600 baud) ? irq = v tst if $fffe and $ffff contain $ff (erased state): ? the external clock is 9.8304 mhz (9600 baud) ?irq = v dd (this can be implemented through the internal irq pullup) if $fffe and $ffff contain $ff (erased state): ? the icg clock is nominal 1.6 mhz (nominal 6300 baud) ?irq = v ss 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
monitor module (mon) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 231 figure 19-8. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, pta1 = 0, ptb4 = 1, and ptb3 = 0? irq = v tst ? pta0 = 1, pta1 = 0, reset vector blank? yes no yes no forced monitor mode normal user mode normal monitor mode invalid user mode no no host sends 8 security bytes is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 19-1 debugging and flash programming (if flash is enabled)
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 232 freescale semiconductor figure 19-9. normal monitor mode circuit figure 19-10. forced monitor mode (irq = v dd ) 10 k 10 k 10 k rst irq pta0 osc1 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? v ss 0.1 f v dd c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd n.c. v cc gnd 1 k ? v dda ptb4 ptb3 pta1 v ssa v dd mc68hc908ey16 9.1 v 9.8304-mhz clock 10 k rst irq pta0 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? 0.1 f c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd n.c. v cc gnd ptb4 ptb3 pta1 mc68hc908ey16 n.c. n.c. n.c. v dd v dda v ss v ssa osc1 9.8304-mhz clock
monitor module (mon) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 233 figure 19-11. forced monitor mode (irq = v ss ) enter monitor mode with pin configuration shown in table 19-1 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the levels on the port pins except pta0 can change. once out of reset, the mcu waits for the host to send eight security bytes (see 19.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecut ive 0s) to the host, indicating that it is ready to receive a command. 19.3.1.1 normal monitor mode if v tst is applied to irq upon monitor mode entry, the bus frequency is a divide-by-four of the input clock. when monitor mode was entered with v tst on irq , the computer operating properly (cop) is disabled as long as v tst is applied to either irq or rst . this condition states that as long as v tst is maintained on the irq pin after entering monitor mode, or if v tst is applied to rst after the initial reset to get into monitor mode (when v tst was applied to irq ), then the cop will be disabled. in the latter situation, after v tst is applied to the rst pin, v tst can be removed from the irq pin in the interest of freeing the irq for normal functionality in monitor mode. 10 k rst irq pta0 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? 0.1 f c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd n.c. v cc gnd ptb4 ptb3 pta1 mc68hc908ey16 n.c. n.c. n.c. v dd v dda v ss v ssa osc1 10 k* * value not critical
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 234 freescale semiconductor 19.3.1.2 forced monitor mode if entering monitor mode without high voltage on irq , then all port b pin requirements and conditions are not in effect. this is to reduce circuit re quirements when performing in-circuit programming. note if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (por). once the reset vector has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. with v dd on irq , an external oscillator of 9.8034 mhz is required for a baud rate of 9600, as the internal bus frequency is automatically set to the external frequency divided by four. table 19-1. monitor mode signal requirements and options mode irq rst reset vector serial communication mode selection icg cop communication speed pta0 pta1 ptb4 ptb3 external clock bus frequency baud rate normal monitor v tst v dd or v tst x1 010offdisabled 9.8304 mhz 2.4576 mhz 9600 forced monitor v dd v dd $ff (blank) 10xxoffdisabled 9.8304 mhz 2.4576 mhz 9600 v ss v dd 1 0 x x on disabled ? nominal 1.6 mhz nominal 6300 user v dd or v ss v dd or v tst not $ff x x x x cn enabled ? nominal 1.6 mhz x mon08 function [pin no.] v tst [6] rst [4] ? com [8] ssel [10] mod0 [12] mod1 [14] ?? osc1 [13] ?? 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 9600 except the forced monitor irq = v ss case. baud rate using external oscillator is bus frequency / 256. 3. external clock is a 9.8304 mhz canned oscillator on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer s ystems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta1 nc 11 12 ptb3 osc1 13 14 ptb4 v dd 15 16 n.c.
monitor module (mon) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 235 with v ss on irq at the monitor entry, the icg is on. in this case, the bus frequency is a nominal 1.6 mhz and the baud rate is a nominal 6300. when the forced monitor mode is entered the cop is always disabled regardless of the state of irq or rst . 19.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 19-2 summarizes the differences be tween user mode and monitor mode. 19.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. transmit and receive baud rates must be identical. figure 19-12. monitor data format 19.3.1.5 break signal a start bit (0) followed by nine 0 bits is a break signal . when the monitor receives a break signal, it drives the pta0 pin high for the duration of approximately two bits and then echoes back the break signal. figure 19-13. break transaction 19.3.1.6 baud rate the communication baud rate is controlled by the crystal frequency or external clock and the state of the ptb5 pin (when irq is set to v tst ) upon entry into monitor mode. if monitor mode was entered with v dd on irq and the reset vector blank, then the baud rate is independent of ptb5. table 19-2. mode differences modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit approximately 2 bits delay before zero echo
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 236 freescale semiconductor table 19-1 also lists external frequencies required to achieve a standard baud rate of 7200 bps. the effective baud rate is the bus fr equency divided by 278. if using a crys tal as the clock source, be aware of the upper frequency limit that the in ternal clock module can handle. see 20.6 control timing for this limit. 19.3.1.7 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. figure 19-14. read transaction figure 19-15. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times
monitor module (mon) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 237 a brief description of each monitor mode command is given in table 19-3 through table 19-8 . table 19-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 19-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 19-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand none data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo from host data return data
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 238 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 19-6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 19-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 19-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo data data from host readsp readsp echo from host sp return sp high low run run echo from host
monitor module (mon) mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 239 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 19-16. stack pointer at monitor mode entry 19.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset wa s not a power-on reset, security remains bypassed and security code entry is not required. see figure 19-17 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight secu rity bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. to determine whether the security code entered is correct, check to see if bit 6 of ram address $40 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the securi ty sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7
development support mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 240 freescale semiconductor figure 19-17. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 5 1 4 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 4 = wait 1 bit time before sending next byte 4 from host from mcu 1 = echo delay, approximately 2 bit times 5 = wait until the monitor rom runs
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 241 chapter 20 electrical specifications 20.1 introduction this section contains preliminary el ectrical and timing specifications. 20.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 20.5 dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd , v ss , and pta0?pta6 and ptc0-ptc1 i 15 ma maximum current for pins pta0?pta6 and ptc0-ptc1 i pta0 ?i pta6 , i ptc0 ?i ptc1 25 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma storage temperature t stg ?55 to +150 c
electrical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 242 freescale semiconductor 20.3 functional operating range 20.4 thermal characteristics 20.5 dc electrical characteristics characteristic symbol value unit operating temperature range t a ?40 to 135 c operating voltage range v dd 5.0 10% v characteristic symbol value unit thermal resistance qfp (32 pins) ja 100 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 x ja w/c average junction temperature t j t a + (p d x ja ) c characteristic (1) symbol min typ (2) max unit output high voltage i load = ?2.0 ma, all i/o pins i load = ?5.0 ma, all i/o pins i load = ?10.0 ma, all i/o pins i load = ?15.0 ma, pta0?pta6/ss and ptc0?ptc1 only v oh v dd ?0.7 v dd ?1.1 v dd ?1.7 v dd ?1.5 v dd ?0.54 v dd ?0.91 v dd ?1.51 v dd ?0.81 ? ? ? ? v output low voltage i load = 1.6 ma, all i/o pins i load = 5.0 ma, all i/o pins i load = 10.0 ma, all i/o pins i load = 15.0 ma, pta0?pta6/ss and ptc0?ptc1 only v ol ? ? ? ? 0.31 0.56 0.99 1.44 0.4 1 1.5 1.8 v input high voltage ? all ports, irq , rst v ih 0.7 x v dd ? v dd + 0.3 v input low voltage ? all ports, irq , rst v il v ss ? 0.3 x v dd v dc injection current, all ports (3) i inj ? 2.0 ? + 2.0 ma total dc current injection (sum of all i/o) i injtot ? 25 + 25 ma ? continued on next page
dc electrical characteristics mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 243 v dd + v dda supply current run (4),(5) wait (5), (6) stop (lvi off) @ 25 c (7) stop (lvi on) @ 25 c stop (lvi off), ?40 c to 135 c stop (lvi on), ?40 c to 135 c i dd ? ? ? ? ? ? 18 5.2 0.83 0.19 3.0 0.19 25 7.0 2.00 0.24 30 0.30 ma ma a ma a ma i/o ports hi-z leakage current (8) i il ?1 ? +1 a input current ? rst , osc1 i in ?1 ? +1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (9) v por 0?100mv por reset voltage (10) v por 0 700 800 mv por rise time ramp rate r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 3.5 v dd + 4.5 v low-voltage inhibit reset, trip falling voltage (11) v tripf 3.90 4.30 4.50 v low-voltage inhibit reset, trip rising voltage (12) v tripr 4.00 4.40 4.60 v low-voltage inhibit reset/recover hysteresis (13) v hys ?0.09? v pullup resistor ? pta0?pta6/ss (14) , irq , rst r pu 24 ? 48 k ? 1. v dd = 5.5 vdc to 4.5 vdc, v ss = 0 vdc, t a = ?40 c to +135 c, unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. some disturbance of the adc accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. 4. run (operating) i dd measured using internal oscillator at its 32-mhz rate. v dd = 5.5 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports co nfigured as inputs. measured with all modules enabled. 5. all measurements taken with lvi enabled. 6. wait i dd measured using internal oscillator at its 1-mhz rate. all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. all ports configured as inputs. 7. stop i dd is measured with no port pin sourcing current; all modul es are disabled. oscstopen option is not selected. 8. pullups and pulldowns are disabled. 9. maximum is highest voltage that power-on reset (por) is guaranteed. 10. maximum is highest voltage that por is possible. 11. these values assume the lvi is operating in 5-v mode (i.e. lvi5or3 bit is set to 1). for 3-v mode (lvi5or3 = 0), values bec ome min: 2.45, typ: 2.60, max: 2.80 12. these values assume the lvi is operating in 5-v mode (i.e. lvi5or3 bit is set to 1). for 3-v mode (lvi5or3 = 0), values bec ome min: 2.55, typ: 2.66, max: 2.80 13. these values assume the lvi is operating in 5-v mode (i.e. lvi5or3 bit is set to 1). for 3-v mode (lvi5or3 = 0), values become typ: 60 14. pta0?pta4 pullup resistors are for interrupts only and are only enabled when the keyboard is in use. characteristic (1) symbol min typ (2) max unit
electrical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 244 freescale semiconductor 20.6 control timing 20.7 internal osc illator characteristics characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v ss unless otherwise noted. symbol min max unit frequency of operation (2) crystal option (extslow = 1) crystal option (extslow = 0) external clock option (3) 2. see chapter 8 internal clock generator (icg) module for more information. 3. no more than 10% duty cycle deviation from 50% f osc 32 1 dc (4) 4. some modules may require a minimum frequency greater t han dc for proper operation. see appropriate table for this information. 100 8 32 khz mhz mhz internal operating frequency f op ?8mhz internal clock period (1/f op )t cyc 125 ? ns r st input pulse width low (5) 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 50 ? ns irq interrupt pulse width low (6) (edge-triggered) 6. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. t ilih 50 ? ns irq interrupt pulse period t ilil note 8 ? t cyc 16-bit timer (7) input capture pulse width input capture period 7. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. 8. the minimum period, t ilil or t tltl , should not be less than the number of cycles it takes to execute the interrupt service routine plus t cyc . t th, t tl t tltl note 8 ? ? ns t cyc characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = ?40 c to +135 c, unless otherwise noted symbol min typ max unit internal oscillator base frequency (2), (3) 2. internal oscillator is selectable through software for a ma ximum frequency. actual frequency will be multiplier (n) x base frequency. 3. f bus = (f intosc / 4) x n when internal clock source selected f intosc 230.4 307.2 384 khz internal oscillator tolerance f osc_tol ?25 ? +25 % internal oscillator multiplier (4) 4. multiplier must be chosen to limit the ma ximum bus frequency of 8 mhz for 4.5-v operation. n1?127?
external oscillator characteristics mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 245 20.8 external osc illator characteristics characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = ?40 c to +135 c, unless otherwise noted symbol min typ max unit external clock option (2)(3) with icg clock disabled with icg clock enabled extslow = 1 (4) extslow = 0 (4) 2. setting extclken configuration option enables osc1 pin for external clock square-wave input. 3. no more than 10% duty cycle deviation from 50% 4. extslow configuration option configures external oscillator for a slow speed crystal and sets the clock monitor circuits of the icg module to expect an external clock frequency that is higher/lower than the internal oscillator base frequency, f intosc. f extosc dc (5) 60 307.2 k 5. some modules may require a minimum frequency greater t han dc for proper operation. see appropriate table for this information. ? ? ? 32 m (6) 307.2 k 32 m (6) 6. mcu speed derates from 32 mhz at v dd = 4.5 vdc hz external crystal options (7)(8) extslow = 1 (4) extslow = 0 (4) 7. setting extclken and extxtalen conf iguration options enables osc1 and osc2 pins for external crystal option. 8. f bus = (f extosc / 4) when external clock source is selected. f extosc 30 k 1 m ? ? 100 k 8 m hz crystal load capacitance (9) 9. crystal manufacturer?s value, see figure 8-3. internal clock generator block diagram . c l ?12.5? pf crystal fixed capacitance (9) c 1 ?15?pf crystal tuning capacitance (9) c 2 ?15?pf extslow = 1 feedback bias resistor (9) series resistor (9) r b r s ? 100 10 330 ? 470 m ? k ? extslow = 0 feedback bias resistor (9) series resistor (9)(10) f extosc =1mhz f extosc =4mhz f extosc =8mhz 10. not required for high-frequency crystals r b r s r s r s ? ? ? ? 1 20 10 0 ? ? ? ? m ? k ? k ? k ?
electrical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 246 freescale semiconductor 20.9 trimmed accuracy of the internal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, can vary as much as 25% due to process, temperature, and voltage. the trimming capability ex ists to compensate for process affects. the remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting). these affects are designed to be minimal, however variati on does occur. better performance is seen with lower settings of n. 20.9.1 trimmed internal cl ock generator characteristics characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2),(3) ?40 c to 85 c ?40 c to 135 c 2. absolute value of variation in ic g output frequency, tr immed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ? ? 2.0 2.5 3.5 5.0 % variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.05 0.08 %/ c variation over voltage (3), (5) 25 c ?40 c to 85 c ?40 c to 135 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? ? 1.0 1.0 1.0 2.0 2.0 2.0 %/v
analog-to-digital converte r (adc) characteristics mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 247 20.10 analog-to-digital co nverter (adc) characteristics characteristic symbol min typ max unit notes supply voltage v dda 4.5 ? 5.5 v v dda should be tied to the same potential as v dd via separate traces input voltages v adin 0? v dda v v adin <= v dda resolution b ad 10 ? 10 bits absolute accuracy a ad ?4 ? +4 lsb includes quantization adc internal clock f adic 500 k ? 1.048 m hz t aic = 1/f adic conversion range r ad v ssa ? v dda v power-up time t adpu 16 ? ? t aic cycles conversion time t adc 16 ? 17 t aic cycles sample time t ads 5? ? t aic cycles monotonicity m ad guaranteed zero input reading z adi 000 ? 003 hex full-scale reading f adi 3fc ? 3ff hex input capacitance c adi ? ? 30 pf not tested v refh /v refl current i vref ?1.6 ? ma absolute accuracy (8-bit truncated mode) a ad ?1 ? + 1 lsb includes quantization zero input reading (8-bit truncated mode) z adi 00 ? 01 hex full-scale reading (8-bit truncated mode) f adi fe ? ff hex quantization error (8-bit truncated mode) ??? +7/8 ?1/8 lsb
electrical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 248 freescale semiconductor 20.11 spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 20-1 and figure 20-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1? t cyc 3 enable lag time t lag(s) 1? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 40 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?40ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 50 50 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
spi characteristics mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 249 figure 20-1. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1
electrical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 250 freescale semiconductor figure 20-2. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1
memory characteristics mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 251 20.12 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to 0. 1?? s flash cumulative program hv period t hv (3) 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv maximum. ?? 4ms flash endurance (4) 4. typical endurance was evaluated for this product fami ly. for additional information on how freescale defines typical endurance , please refer to engineering bulletin eb619. ? 10 k 100 k ? cycles flash data retention time (5) 5. typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25c using the arrhenius equation. for additional information on how freescale defines typical data retention , please refer to engineering bulletin eb618. 6. in the 125c to 135c temperature r ange, the flash is guaranteed as read only. ? 15 100 ? years
electrical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 252 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 253 chapter 21 ordering information and mechanical specifications 21.1 introduction this section contains ordering numbers for mc68hc 908ey16. an example of the device numbering system is given in figure 21-1 . in addition, this section gives the pac kage dimensions for the 32-pin quad flat pack (qfp). 21.2 mc order numbers figure 21-1. device numbering system table 21-1. mc order numbers mc order number (1) 1. fa = quad flat pack operating temperature range mc68hc908ey16kfa ?40c to +135c mc68hc908ey16mfa ?40c to +125c mc68hc908ey16vfa ?40c to +105c mc68hc908ey16cfa ?40c to +85c m c 6 8 h c 9 0 8 e y 1 6 x x x e family package designator temperature range pb free
ordering information and mechanical specifications mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 254 freescale semiconductor 21.3 32-pin qfp (case number 873) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. u b l detail a l ?a? 32 25 24 16 17 18 9 v s a?b m 0.20 (0.008) d s c s a?b m 0.20 (0.008) d s h a?b 0.05 (0.002) s a?b m 0.20 (0.008) d s c a?b 0.05 (0.002) s a?b m 0.20 (0.008) d s h ?d? a s ?b? ?c? seating plane ?h? datum plane m g detail c m h c e 0.01 (0.004) ?h? datum plane t detail c r k q x detail a b b p ?a?, ?b?, ?d? s a?b m 0.20 (0.008) d s c j f n d section b?b base metal view rotated 90 clockwise dim min max min max inches millimeters a 6.95 0.274 0.280 b 6.95 7.10 0.274 0.280 c 1.40 1.60 0.055 0.063 d 0.273 0.373 0.010 0.015 e 1.30 1.50 0.051 0.059 f 0.273 ??? 0.010 ??? g 0.80 bsc 0.031 bsc h ??? 0.20 ??? 0.008 j 0.119 0.197 0.005 0.008 k 0.33 0.57 0.013 0.022 l 5.6 ref 0.220 ref m 6 8 6 8 n 0.119 0.135 0.005 0.005 p 0.40 bsc 0.016 bsc q 5 10 5 10 r 0.15 0.25 0.006 0.010 s 8.85 9.15 0.348 0.360 t 0.15 0.25 0.006 0.010 u 5 11 5 11 v 8.85 9.15 0.348 0.360 x 1.00 ref 0.039 ref 7.10
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 255 appendix a mc68hc908ey8 a.1 introduction the mc68hc908ey8 is a member of the low-cos t, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. the information contained in this document pertains to the mc68hc908ey8 with the exceptions shown in this appendix. a.2 block diagram see figure a-1 . a.3 memory the memory map, shown in figure a-2 , includes: 8 kbytes of flash memory, 7680 bytes of user space 512 bytes of random-access memory (ram) 36 bytes of user-defined vectors 310 bytes of monitor routines in read-only memory (rom) 1024 bytes of integrated flash burn-in routines in rom the flash memory is an array of 7680 bytes with an additional 36 bytes of user vectors and one byte used for block protection. the flash is organized in ternally as an 8192-word by 8-bit complementary metal-oxide semiconductor (cmos) page erase, byte (8-bit) program embedded flash memory. each page consists of 64 bytes. the page erase operation erases all words within a page. a page is composed of two adjacent rows. a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 256 freescale semiconductor figure a-1. mc68hc908ey8 block diagram single breakpoint break module 2-channel timer interface module b 5-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user flash user ram monitor rom user flash vector space single external irq module internal bus interrupt module computer operating properly module v dda 10-bit analog-to-digital converter module v ssa 2-channel timer interface module a security module power v ss v dd power-on reset module flash programming (burn-in) rom 24 internal system integration module internal clock generator module osc1 rst ddre port e ddrc port c ddrb port b ddra port a irq serial peripheral interface module ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso pte0/txd pte1/rxd ptd0/tach0 ptd1/tach1 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 pta5/spsck ptb0/ad0 enhanced serial communication interface module configuration register module ddrd port d osc2 periodic wakeup timebase module arbiter module prescaler module pta6/ss v refh v refl bemf module 1024 bytes 64 bytes 7680 bytes 384 bytes 310 bytes 36 bytes
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 257 $0000 i/o registers 64 bytes $fe08 flash control register (flcr) $fe09 break address register high (brkh) $003f $fe0a break address register low (brkl) $0040 ram 384 bytes $fe0b break status and control register (brkscr) $fe0c lvi status register (lvisr) $01bf $fe0d reserved 3 bytes $01c00 unimplemented 3648 bytes $fe0f $0fff $fe10 reserved 16 bytes reserved for compatibility with monitor code for a-family parts $1000 reserved for integrated flash burn-in routines 1024 bytes $fe1f $13ff $fe20 monitor rom 310 bytes $1400 unimplemented 53,334 bytes ff55 $dfff ff56 unimplemented 40 bytes $e000 flash memory 7680 bytes ff7d $fdff $ff7e flash block protect register (flbpr) $fe00 sim break status register (sbsr) $ff7f unimplemented 93 bytes $fe01 sim reset status register (srsr) $fe02 reserved $ffdb $fe03 sim break flag control register (sbfcr) $ffdc flash vectors 36 bytes $fe04 reserved $fe05 reserved $ffff $fe06 reserved note: locations $fff6?$fffd are reserved for eight security bytes. $fe07 reserved for flash test control register (fltcr) figure a-2. mc68hc908ey8 memory map
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 258 freescale semiconductor a.4 mc order numbers figure a-3. device numbering system table a-1. mc order numbers mc order number (1) 1. fa = quad flat pack operating temperature range mc68hc908ey8kfa ?40c to +135c mc68hc908ey8mfa ?40c to +125c mc68hc908ey8vfa ?40c to +105c mc68hc908ey8cfa ?40c to +85c m c 6 8 h c 9 0 8 e y 8 x x x e family package designator temperature range pb free
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 259 glossary a ? see ?accumulator (a).? accumulator (a) ? an 8-bit general-purpose register in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode ? a mode of pll operation during start up before the pll locks on a frequency. also see "tracking mode." address bus ? the set of wires that the cpu or dma uses to read and write memory locations. addressing mode ? the way that the cpu determines the operand address for an instruction. the m68hc08 cpu has 16 addressing modes. alu ? see ?arithmetic logic unit (alu).? arithmetic logic unit (alu) ? the portion of the cpu that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous ? refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate ? the total number of bits transmitted per unit of time. bcd ? see ?binary-coded decimal (bcd).? binary ? relating to the base 2 number system. binary number system ? the base 2 number system, having two di gits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (bcd) ? a notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) bit ? a binary digit. a bit has a value of either 0 or 1. branch instruction ? an instruction that causes the cpu to continue processing at a memory location other than the next sequential address. break module ? a module in the m68hc08 family. the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint ? a number written into the break address registers of the break module. when a number appears on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi).
glossary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 260 freescale semiconductor break interrupt ? a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus ? a set of wires that transfers logic signals. bus clock ? the bus clock is derived from the cgmout output from the cgm. the bus clock frequency, f op , is equal to the frequency of the oscill ator output, cgmxclk, divided by four. byte ? a set of eight bits. c ? the carry/borrow bit in the condition code regi ster. the cpu08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). ccr ? see ?condition code register.? central processor unit (cpu) ? the primary functioning unit of any computer system. the cpu controls the execution of instructions. cgm ? see ?clock generator module (cgm).? clear ? to change a bit from 1 to 0; the opposite of set. clock ? a square wave signal used to synchronize events in a computer. clock generator module (cgm) ? a module in the m68hc08 fam ily. the cgm generates a base clock signal from which the system clocks are derived. th e cgm may include a crystal oscillator circuit and or phase-locked loop (pll) circuit. comparator ? a device that compares the magnitude of tw o inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (cop) ? a counter module in the m68hc08 family that resets the mcu if allowed to overflow. condition code register (ccr) ? an 8-bit register in the cpu08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit ? one bit of a register manipulated by software to control the operation of the module. control unit ? one of two major units of the cpu. the control unit contains logic functions that synchronize the machine and direct various operations. the control unit decodes instructions and generates the internal control signals that perfo rm the requested operations. the outputs of the control unit drive the execution uni t, which contains the arithmetic logic unit (alu), cpu registers, and bus interface. cop ? see "computer operating properly module (cop)." counter clock ? the input clock to the tim counter. this clock is the output of the tim prescaler. cpu ? see ?central processor unit (cpu).? cpu08 ? the central processor unit of the m68hc08 family.
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 261 cpu clock ? the cpu clock is derived from the cgmo ut output from the cgm. the cpu clock frequency is equal to the frequency of the oscillator output, cgmxclk, divided by four. cpu cycles ? a cpu cycle is one period of the internal bu s clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. the length of time required to execute an instruction is measured in cpu clock cycles. cpu registers ? memory locations that are wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the information in these registers. the cpu registers in an m68hc08 are: a (8-bit accumulator) h:x (16-bit index register) sp (16-bit stack pointer) pc (16-bit program counter) ccr (condition code register containing the v, h, i, n, z, and c bits) csic ? customer-specified integrated circuit cycle time ? the period of the operating frequency: t cyc =1/f op . decimal number system ? base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) ? a m68hc08 family module th at can perform data transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma transfe rs are faster and more code-efficient than cpu interrupts. dma ? see "direct memory access module (dma)." dma service request ? a signal from a peripheral to the dm a module that enables the dma module to transfer data. duty cycle ? a ratio of the amount of time the signal is on vers us the time it is off. duty cycle is usually represented by a percentage. eeprom ? electrically erasable, programmable, read-onl y memory. a nonvolatile type of memory that can be electrically reprogrammed. eprom ? erasable, programmable, read-only memory. a nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception ? an event such as an interrupt or a rese t that stops the sequential execution of the instructions in the main program. external interrupt module (irq) ? a module in the m68hc08 fami ly with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch ? to copy data from a memory location into the accumulator. firmware ? instructions and data programmed into nonvolatile memory. free-running counter ? a device that counts from zero to a predetermined number, then rolls over to zero and begins counting again.
glossary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 262 freescale semiconductor full-duplex transmission ? communication on a channel in wh ich data can be sent and received simultaneously. h ? the upper byte of the 16-bit index register (h:x) in the cpu08. h ? the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instruction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal ? base 16 numbering system that uses the digits 0 through 9 and the letters a through f. high byte ? the most significant eight bits of a word. illegal address ? an address not within the memory map illegal opcode ? a nonexistent opcode. i ? the interrupt mask bit in the condition code regist er of the cpu08. when i is set, all interrupts are disabled. index register (h:x) ? a 16-bit register in the cpu08. the upper byte of h:x is called h. the lower byte is called x. in the indexed addressing modes, the cpu uses the c ontents of h:x to determine the effective address of the operand. h:x can also serve as a temporary data storage location. input/output (i/o) ? input/output interfaces between a computer system and the external world. a cpu reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions ? operations that a cpu can perform. inst ructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode and its associated operand(s) and instruction. interrupt ? a temporary break in the sequential execut ion of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request ? a signal from a peripheral to the cpu intended to cause the cpu to execute a subroutine. i/o ? see ?input/output (i/0).? irq ? see "external interrupt module (irq)." jitter ? short-term signal instability. latch ? a circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ? the time lag between instruction completion and data movement. least significant bit (lsb) ? the rightmost digit of a binary number. logic 1 ? a voltage level approximately equal to the input power voltage (v dd ).
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 263 logic 0 ? a voltage level approximately equal to the ground voltage (v ss ). low byte ? the least significant eight bits of a word. low voltage inhibit module (lvi) ? a module in the m68hc08 family that monitors power supply voltage. lvi ? see "low voltage inhibit module (lvi)." m68hc08 ? a freescale family of 8-bit mcus. mark/space ? the logic 1/logic 0 convention used in formatting data in serial communication. mask ? 1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option ? a optional microcontroller feature that the customer chooses to enable or disable. mask option register (mor) ? an eprom location containing bits that enable or disable certain mcu features. mcu ? microcontroller unit. see ?microcontroller.? memory location ? each m68hc08 memory location holds one byte of data and has a unique address. to store information in a memory location, the cp u places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the selected memory location places its data onto the data bus. memory map ? a pictorial representation of all memory locations in a computer system. microcontroller ? microcontroller unit (mcu). a complete computer system, including a cpu, memory, a clock oscillator, and input/output (i/o) on a single integrated circuit. modulo counter ? a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom ? a section of rom that can execute co mmands from a host computer for testing purposes. mor ? see "mask option register (mor)." most significant bit (msb) ? the leftmost digit of a binary number. multiplexer ? a device that can select one of a number of inputs and pass the logic level of that input on to the output. n ? the negative bit in the condition code register of the cpu08. the cpu sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble ? a set of four bits (half of a byte). object code ? the output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code.
glossary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 264 freescale semiconductor opcode ? a binary code that instructs the cpu to perform an operation. open-drain ? an output that has no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand ? data on which an operation is performed. us ually a statement consists of an operator and an operand. for example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator ? a circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. otprom ? one-time programmable read-only memory. a nonvolatile type of memory that cannot be reprogrammed. overflow ? a quantity that is too large to be contained in one byte or one word. page zero ? the first 256 bytes of memory (addresses $0000?$00ff). parity ? an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd parity, every byte is expected to have an odd number of logic 1s. in an even parity system, every byte should have an even numbe r of logic 1s. in the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. a parity checker in the receiver c ounts the number of logic 1s in each byte. the parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. pc ? see ?program counter (pc).? peripheral ? a circuit not under direct cpu control. phase-locked loop (pll) ? a oscillator circuit in which the freque ncy of the oscillator is synchronized to a reference signal. pll ? see "phase-locked loop (pll)." pointer ? pointer register. an index register is someti mes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity ? the two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, v dd and v ss . polling ? periodically reading a status bit to monitor the condition of a peripheral device. port ? a set of wires for communicating with off-chip devices. prescaler ? a circuit that generates an output signal relat ed to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program ? a set of computer instructions that caus e a computer to perform a desired operation or operations. program counter (pc) ? a 16-bit register in the cpu08. the pc register holds the address of the next instruction or operand that the cpu will use.
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 265 pull ? an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. pullup ? a transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width ? the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ? controlled variation (modulation) of the pulse width of a signal with a constant frequency. push ? an instruction that copies the contents of the accumulator to the stack ram. the stack ram address is in the stack pointer. pwm period ? the time required for one complete cycle of a pwm waveform. ram ? random access memory. all ram locations can be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. rc circuit ? a circuit consisting of capacitors and resistors having a defined time constant. read ? to copy the contents of a memory location to the accumulator. register ? a circuit that stores a group of bits. reserved memory location ? a memory location that is used only in special factory test modes. writing to a reserved location has no effect. reading a reserved location returns an unpredictable value. reset ? to force a device to a known condition. rom ? read-only memory. a type of memory that can be read but cannot be changed (written). the contents of rom must be specified before manufacturing the mcu. sci ? see "serial communication interface module (sci)." serial ? pertaining to sequential transmission over a single line. serial communications interface module (sci) ? a module in the m68hc08 family that supports asynchronous communication. serial peripheral interface module (spi) ? a module in the m68hc08 family that supports synchronous communication. set ? to change a bit from logic 0 to logic 1; opposite of clear. shift register ? a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed ? a binary number notation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. the other sev en bits indicate the magnitude of the number. software ? instructions and data that control the operation of a microcontroller. software interrupt (swi) ? an instruction that causes an interrupt and its associated vector fetch.
glossary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 266 freescale semiconductor spi ? see "serial peripheral interface module (spi)." stack ? a portion of ram reserved for storage of cpu register contents and subroutine return addresses. stack pointer (sp) ? a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. start bit ? a bit that signals the beginning of an asynchronous serial transmission. status bit ? a register bit that indicates the condition of a device. stop bit ? a bit that signals the end of an asynchronous serial transmission. subroutine ? a sequence of instructions to be used more than once in the course of a program. the last instruction in a subroutine is a return from subroutine (rts) instruction. at each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is used to call the subroutine. the cpu leaves the flow of the main program to execute the instructions in the subroutine. when the rts instruction is executed, the cpu returns to the main program where it left off. synchronous ? refers to logic circuits and operations that are synchronized by a common reference signal. tim ? see "timer interface module (tim)." timer interface module (tim) ? a module used to relate events in a system to a point in time. timer ? a module used to relate events in a system to a point in time. toggle ? to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ? mode of low-jitter pll operation during wh ich the pll is locked on a frequency. also see "acquisition mode." two?s complement ? a means of performing binary subtraction using addition techniques. the most significant bit of a two?s complement number indica tes the sign of the number (1 indicates negative). the two?s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered ? utilizes only one register for data; new data overwrites current data. unimplemented memory location ? a memory location that is not used. writing to an unimplemented location has no effect. reading an unimplemented loca tion returns an unpredictable value. executing an opcode at an unimplemented location causes an illegal address reset. v ?the overflow bit in the condition code register of the cpu08. the cpu08 sets the v bit when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable ? a value that changes during the course of program execution. vco ? see "voltage-controlled oscillator."
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 267 vector ? a memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (vco) ? a circuit that produces an osc illating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform ? a graphical representation in which the ampl itude of a wave is plotted against time. wired-or ? connection of circuit outputs so that if any output is high, the connection point is high. word ? a set of two bytes (16 bits). write ? the transfer of a byte of data from the cpu to a memory location. x ? the lower byte of the index register (h:x) in the cpu08. z ? the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00.
glossary mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 268 freescale semiconductor
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 269 revision history changes from rev 9.0 published in august 2005 to rev 10 published in october 2005 changes from rev 8.0 publis hed in july 2005 to rev 9 published in august 2005 section page (in rev 10) description of change configuration registers (config1 and config2) 57 figure 5-1. configuration register 2 (config2) ? corrected name for bit 6 to escibdsrc. system integration module (sim) 159 14.3.2.5 forced monitor mode entry reset (menrst) ? corrected erased value from $00 to $ff. timebase module (tbm) 189 figure 16-1. timebase block diagram ? corrected label from tbmclksel to tmbclksel. section page (in rev 9) description of change throughout n/a updated to meet freescale identity guidelines. memory 32 changed adrh register bit names at address location $003d from adch9 and adch8 to ad9 and ad8 respectively. analog-to-digital converter (adc) module 53 table 3-2. adc clock divide ratio ? changed last table entry under adc clock rate from adc input clock 6 to adc input clock 16. computer operating properly (cop) module 63 6.6 monitor mode ? changed v dd = v tst is present to v tst is present. keyboard interrupt (kbd) module 110 10.7.2 keyboard interrupt enable register ? in bit definition changed pdx to kbdx. low-voltage inhibit (lvi) module 112 11.3.1 polled lvi operation ? changed lvirstd bit must be at 0 to enable lvi resets to lvirstd bit must be at 1 to disable lvi resets 113 11.5.2 stop mode ? changed lvipwrd bit in the configuration register programmed to 0 to lvipwrd bit in t he configuration register programmed to 1 input/output (i/o) ports (ports) 117 figure 12-4. port b data register (ptb) ? changed atd7?atd0 to ad7?ad0 in both the bit descriptions and alternative function blocks. enhanced serial communications interface (esci) module 142 13.8.3 esci control register 3 ? in the bit description for peie, changed esci receiver cpu interrupt request to esci error cpu interrupt request 143 13.8.4 esci status register 1 ? in the bit description for idle, changed esci error cpu interrupt request to esci receiver cpu interrupt request.
revision history mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 270 freescale semiconductor changes from rev 7.0 publis hed in march 2004 to rev 8 published in july 2005 section page (in rev 8) description of change memory 26 on added icgt at $ff80 in figure 2-1 and figure 2-2. internal clock generator (icg) module 80 removed overbars from osc1 and osc2 in figure 8-1. 103 added 8.7.4 icg trim value. low-voltage inhibit (lvi) module 117 new introductory paragraph in 11.3 functional description. modified sections 11.3.1, 11.3.2, 11.5.1, 11.5.2. 118 changed ?to disable lvi resets? to ?to enable lvi resets? in 11.3.1 polled lvi operation. deleted ?for 32 to 40 cgmxclk cycles? from last sentence in 11.3.4 lvi status register. input/output (i/o) ports (ports) 129 modified figure 12-13. enhanced serial communications interface (esci) module 158 changed ?11-bit? to ?13-bit? and ?12-bit? to ?14-bit? in table 13-6. 163, 164 changed ?...is clocked with one half...? to ?...is clocked with one quarter...? system integration module (sim) 170 new introductory paragraph in 14.3.1 external pin reset. 170 updated and moved table 14-2. serial peripheral interface (spi) module 186 changed ss pin to from input/output to input only in figure 15-2. timer interface a (tima) module 216 changed ptex/tchx to ptdx/tchx in figure 17-3. 221 added para to note after tstop ? tima stop bit 225 new table 17-2. timer interface b (timb) module 232 changed ?tchxh?tchxl? to ?tbchxh? tbchxl? in 18.3.2 input capture. 234 changed ptex/tchx to ptbx/tchx in figure 18-3. 239 added para to note after tstop ? timb stop bit 243 new table 18-2. development support 247 whole chapter replaced with new version. electrical specifications 267 changed values of hi-z leakage current in 20.5 dc electrical characteristics. 269 changed specification for resistance and capacitance values for extslow = 1 and extslow = 0, in 20.8 external oscillator characteristics. appendix a mc68hc908ey8 279 added appendix describing the mc68hc908ey8
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 271 changes from rev 6.0 publis hed in january 2004 to rev 7.0 published in march 2004 changes from rev 5.0 published in september 2003 to rev 6.0 published in january 2004 section page (in rev 7.0) description of change general description 19 changed ?25 percent accuracy with trim capability to 2 percent? to ?25 percent accuracy with a trimming capability of better than 1 percent? (two instances). memory 35 changed ?brkscr? to ?bscr?. memory 37 added sentence about 125c to 135c temperature range. analog-to-digital converter (adc) module 50 changed ?ms? to ? s? (two instances). computer operating properly (cop) module 72 changed ?coprs = 1? to ?coprs = 0?. internal clock generator (icg) module 89 changed ?7 percent? to ?3.5 percent? (two instances). internal clock generator (icg) module 116 replaced ?to +/-2%? with a cross-reference. input/output (i/o) ports (ports) 141 added note. enhanced serial communications interface (esci) module 177 modified note to include reference to prescaler divisor fine adjust (pdfa). timer interface a (tima) module 244 deleted ?port b or?. development support 265 on whole section on development support replaced. electrical specifications 284 on changed ?125c? to ?135c? on pages 282, 283 (3), 285 (2), 286 (2). added note 6 on page 291. electrical specifications 286 modified the first row of the table to show two crystal options, instead of one.. electrical specifications 288 modified the typical a nd maximum values in the first row of the table. ordering information and mechanical specifications 295 appended row to table 21-1. appendix a. mc68hc908ey8 297 appended row to table a-1. appendix a. mc68hc908ey8 298, 299 change ram size from 512 to 384 and adjusted addresses accordingly. section page (in rev 6.0) description of change memory 40 removed erroneous caution note to 2.6.3 flash mass erase operation updated 2.6.5 flash block protection and 2.6.6 flash block protect register appendix a. mc68hc908ey8 295 added appendix describing the mc68hc908ey8
revision history mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 272 freescale semiconductor changes from rev 4.0 published in february 2003 to rev 5. 0 published in september 2003 changes from rev 3.0 publishe d in november 2002 to re v 4.0 published in february 2003 changes from rev 2.0 published in may 2002 to rev 3.0 publi shed in november 2002 section page (in rev 5.0) description of change throughout n/a reformatted document to current publications standards memory 39 updated procedures for flash page erase operation 40 updated procedures for flash mass erase operation computer operating properly (cop) module 69 updated block diagram system integration module (sim) 196 updated definitio n for sbsw bit of sim brea k status register (sbsr) development support 263 updated def inition for sbsw bit of sim break status re gister (sbsr) electrical specifications 289 updated memory characteristics table with new information corrected notes to supply currents in 20.5 dc electrical characteristics. section page (in rev 4.0) description of change electrical specifications 280 281 285 updated parameters for output high voltage (v oh ), output low voltage (v ol ) and supply current (i dd ) updated parameters for low voltage inhibit reset: v tripf , v tripr and v hys . updated parameters for adc absolute accuracy, zero input reading, full-scale reading, zero input reading (8-bit truncated mode) and full-scale reading (8-bit truncated mode). section page (in rev 3.0) description of change memory map 50 lvi5or3 bit added to config1 56 esci vectors re-ordered flash memory 62 minimum changed to 4ms in step 6. system integration module (sim) 93 94 106 figure 6-5 updated figure 6-6 updated code example removed from sbsw description internal clock generator (icg) module 118 137 ptb6/osc1 and ptb7/osc2 correct ed to ptc4/osc1 and ptc3/osc2 respectively configuration registers (config1 & config2) 151 copd corrected to coprs in coprs bit description 148 152 lvi5or3 bit added to config1 and default reset state changed to 0 lvi5or3 description added break module (brk) 162 code exampl e removed from sbsw description computer operating properly (cop) module 178 copl corrected to coprs in figure 11-1 179 copl corrected to coprs in top paragraph 180 copl corrected to co prs in section 11.4.8 181 irq1 corrected to irq low-voltage inhibit (lvi) module 183 3rd bullet added to features external interrupt (irq) 190 191 irq1 corrected to irq
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 273 changes from rev 1.0 publis hed on 17 april 2002 to r ev 2.0 published in may 2002 3v option removed. ptb5 frequency divider function removed. bemf section moved from appendix to section 18 . changes from rev 0.4 published internally on 9 april 2002 to rev 1. 0 published on 17 april 2002 change in revision number only to denote external release version. changes from rev 0.3 publis hed on 6 september 2001 to r ev 0.4 published internally on 9 april 2002 enhanced serial communications interface (esci) module 233 237 extra paragraph added describing linr bit functionality in lin version 1.2 systems ?sci clock source? changed to ?frequency of the sci clock source? in baud rate equation and description electrical specifications 382 383 output high voltage, i load =?10.0ma changed to ?5.0ma output low voltage, i load =10.0ma changed to 5.0ma footnotes 11, 12 and 13 added section page (in rev 2.0) description of change memory map 50 escibdsrc bit added to config2 configuration registers (config1 & config2) 148 escibdsrc bit added to config2 with bit description enhanced serial communications interface (esci) module 200 baud rate selection sentence added to sections 14.5 and 14.5.2 and after table 14-10. section page (in rev 0.4) description of change memory map 43 reserved port register bits redefined as unimplemented flash memory 62 note added about erasing last flash page 65 removed last two sentences of flash block protection description system integration module (sim) 92 rst description added configuration registers (config1 & config2) 149 ptb7 changed to ptc3 monitor rom (mon) 169 table 10-1. mode selection added 170 added sentence about forced monitor mode updated first note in section 10.5.1 170 ptb5 column added to table 10-2 171 ptb5 pin added to figure 10-1 section page (in rev 3.0) description of change
revision history mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 274 freescale semiconductor changes from rev 0.2 published on 1 august 2001 to rev 0.3 published on 6 september 2001 enhanced serial communications interface (esci) module 210 238 243 and 244 note added regarding length of break character when followed by an idle. prescale bits renamed aclk = 0 description changed timer interface a (tima) module 279 ? 301 several updates for clarification timer interface b (timb) module 303 ? 326 several updates for clarification analog-to-digital converter (adc) module 345 354 355 reserved register bits redefined as unimplemented table 20-1 updated to show all unused combinations left justified mode description corrected input/output (i/o) ports 361 ? 376 366 reserved register bits redefined as unimplemented port b description updated preliminary electrical specifications 382 and 384 382 and 384 382 and 384 386 391 changes to: hi-z leakage current input current monitor mode entry voltage external clock frequency of operation flash page erase time section page (in rev 0.3) description of change memory map 50 $001e tmbcl ksel and ssbpuen b bits added configuration registers (config1 & config2) 150 $001e tmbclksel an d ssbpuenb bits added 152 corrections to table 8-1: ptb6 to ptc4 and ptb7 to ptc3 low-voltage inhibit (lvi) module 188 figure 12-1 updated, digital filter removed 189 false reset protection text updated 190 table 12-1 updated 191 references to digital filter removed timer interface a (tima) module 280 external clock input removed from features timer interface b (timb) module 304 external clock input removed from features timebase module (tbm) 336 divide-by-128 replaced by divide-by-1024 337 figure 19-1 updated 338 note added after table 19-1 analog-to-digital converter (adc) module 345 ptc and cx removed from figure 20-1 347 adcr changed to adclk preliminary electrical specifications 384 and 386 control timing specifications added 388 and 392 spi characteristics added 391 flash read bus clock frequency changed to 8 mhz section page (in rev 0.4) description of change
mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 freescale semiconductor 275 changes from rev 0.0 publis hed on 17 july 2001 to rev 0.2 published on 1 august 2001 section page (in rev 0.2) description of change general description 34 third bullet in standard features list changes to: 8-mhz internal bus frequency at 5v, 4mhz at 3v 37 bemf module added to block diagram memory map 48 bemf register added 53 register addresses changed for adc: $003b is now reserved adscr is now $003c adrh is now $003d adrl is now $003e 54 reset value of $003f corrected to $04 flash memory 68 several corrections made to table 4-1 monitor rom (mon) 168, 172 erased flash locations corrected to $ff keyboard interrupt (kbd) module 330 keyboard interrupt vector corrected to $ffe4 and $ffe5 analog-to-digital converter (adc) module 352 address of adscr is now $003c 355 address of adrh is now $003d register description now includes left justified mode 358 address of adrl is now $003e for right justified mode as well as 8-bit mode register description now includes left justified mode 359 reset value of $003f corrected to $04 input/output (i/o) ports 361 bemf register added to figure 21-1 preliminary electrical specifications 383 dc injection current specifications corrected bemf module 401 new appendix
revision history mc68hc908ey16 mc68hc908ey8 data sheet, rev. 10 276 freescale semiconductor

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